switch(get_ia32_op_type(n)) {
case ia32_Normal:
- if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ if (is_ia32_ImmConst(n)) {
lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
}
+ else if (is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
+ }
else {
const arch_register_t *in1 = get_in_reg(n, 2);
const arch_register_t *in2 = get_in_reg(n, 3);
get_ia32_cnst(n)); /* tell the assembler to store it's address. */
}
else {
- const arch_register_t *in1 = get_in_reg(n, 2);
- ir_mode *mode = get_ia32_res_mode(n);
- const char *in_name;
+ const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
+ ir_mode *mode = get_ia32_res_mode(n);
+ const char *in_name;
mode = mode ? mode : get_ia32_ls_mode(n);
in_name = ia32_get_reg_name_for_mode(env, mode, in1);
case ia32_AddrModeD:
snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
break;
+ case ia32_AddrModeS:
+ /*
+ Mulh is emitted via emit_unop
+ imul [MEM] means EDX:EAX <- EAX * [MEM]
+ */
+ assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
default:
assert(0 && "unsupported op type");
}
int had_output = 0;
char *s;
const char *p;
- int size;
static struct obstack *obst = NULL;
ir_mode *mode = get_ia32_ls_mode(n);
if (had_output)
obstack_printf(obst, "] ");
- size = obstack_object_size(obst);
- s = obstack_finish(obst);
- s[size - 1] = '\0';
+ obstack_1grow(obst, '\0');
+ s = obstack_finish(obst);
return s;
}
instr = "sub";
}
- /* in case of a PsiCondSet use mov because it doesn't affect the eflags */
- if (is_ia32_PsiCondSet(irn)) {
- snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
- }
- else {
- snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s, %%%s", instr, arch_register_get_name(out), arch_register_get_name(out));
- }
-
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
- IA32_DO_EMIT(irn);
-
if (is_ia32_CmpSet(irn)) {
lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
}
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
IA32_DO_EMIT(irn);
+ /* use mov to clear target because it doesn't affect the eflags */
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+ IA32_DO_EMIT(irn);
+
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
IA32_DO_EMIT(irn);
/* fill the table structure */
tbl.label = xmalloc(SNPRINTF_BUF_LEN);
- tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, "JMPTBL_");
+ tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
tbl.defProj = NULL;
tbl.num_branches = get_irn_n_edges(irn);
tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
/**
* Emit movsb/w instructions to make mov count divideable by 4
*/
-static void emit_CopyB_prolog(FILE *F, int rem, int size) {
+static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- fprintf(F, "\t/* memcopy %d bytes*/\n", size);
+ ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward*/");
- IA32_DO_EMIT(NULL);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
switch(rem) {
case 1:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
break;
case 2:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
break;
case 3:
+ IA32_DO_EMIT(NULL);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
IA32_DO_EMIT(NULL);
* Emit rep movsd instruction for memcopy.
*/
static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
- tarval *tv = get_ia32_Immop_tarval(irn);
- int rem = get_tarval_long(tv);
- ir_node *size_node = get_irn_n(irn, 2);
- int size;
+ FILE *F = emit_env->out;
+ tarval *tv = get_ia32_Immop_tarval(irn);
+ int rem = get_tarval_long(tv);
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- /* beware: size_node could be a be_Copy to fulfill constraints for ecx */
- size_node = be_is_Copy(size_node) ? be_get_Copy_op(size_node) : size_node;
- size = get_tarval_long(get_ia32_Immop_tarval(size_node));
-
- emit_CopyB_prolog(F, rem, size);
+ emit_CopyB_prolog(F, irn, rem);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
FILE *F = emit_env->out;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- emit_CopyB_prolog(F, size & 0x3, size);
+ emit_CopyB_prolog(F, irn, size & 0x3);
size >>= 2;
while (size--) {
assert(0 && "unsupported Conv_I2I");
}
- switch(get_ia32_op_type(irn)) {
+ switch(get_ia32_op_type(irn)) {
case ia32_Normal:
in_reg = get_in_reg(irn, 2);
out_reg = get_out_reg(irn, 0);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
}
else {
- lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "%1D", get_irn_n(irn, be_pos_Call_ptr));
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
}
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
FILE *F = emit_env->out;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2;
+ const arch_register_class_t *cls1, *cls2;
+
+ in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
+ in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
+
+ cls1 = arch_register_get_class(in1);
+ cls2 = arch_register_get_class(in2);
+
+ assert(cls1 == cls2 && "Register class mismatch at Perm");
+
+ if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
+ "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ assert(0 && "Perm with vfp should not happen");
+ }
+ else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
+ assert(0 && "Perm with st(X) should not happen");
+ }
- lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
IA32_DO_EMIT(irn);
}
* Emits code for Constant loading.
*/
static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
- FILE *F = env->out;
- char cmd_buf[256], cmnt_buf[256];
- const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ FILE *F = env->out;
+ char cmd_buf[256], cmnt_buf[256];
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
- if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
+ if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
const char *instr = "xor";
if (env->isa->opt_arch == arch_pentium_4) {
/* P4 prefers sub r, r, others xor r, r */
instr = "sub";
}
- lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
- }
- else {
- if (get_ia32_op_type(n) == ia32_SymConst) {
- lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
- }
+ lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+ }
+ else {
+ if (get_ia32_op_type(n) == ia32_SymConst) {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+ }
else {
- lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
- lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
}
- }
- lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+ }
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
}
static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
- FILE *F = env->out;
- const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
- lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
}
projects / libfirm / blobdiff