* |_| |_|
*************************************************************/
+/**
+ * returns true if a node has x87 registers
+ */
+static int has_x87_register(const ir_node *n)
+{
+ return get_irn_op(n)->flags & (irop_flag_machine << 1);
+}
+
/* We always pass the ir_node which is a pointer. */
static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
return lc_arg_type_ptr;
*/
static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
const arch_register_t *reg;
- const char *name;
- static char *buf = NULL;
- int len;
if (in_out == IN_REG) {
reg = get_in_reg(irn, pos);
+
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ /* FIXME: works for binop only */
+ assert(2 <= pos && pos <= 3);
+ reg = get_ia32_attr(irn)->x87[pos - 2];
+ }
}
else {
/* destination address mode nodes don't have outputs */
}
reg = get_out_reg(irn, pos);
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+ reg = get_ia32_attr(irn)->x87[pos + 2];
}
-
- name = arch_register_get_name(reg);
-
- if (buf) {
- free(buf);
- }
-
- len = strlen(name) + 2;
- buf = xcalloc(1, len);
-
- snprintf(buf, len, "%%%s", name);
-
- return buf;
+ return arch_register_get_name(reg);
}
/**
buf = get_ia32_reg_name(X, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
+ /* append the stupid % to register names */
+ lc_appendable_chadd(app, '%');
return lc_appendable_snadd(app, buf, strlen(buf));
}
attr = get_ia32_attr(X);
buf = attr->x87[nr]->name;
+ lc_appendable_chadd(app, '%');
return lc_appendable_snadd(app, buf, strlen(buf));
}
const arch_register_t *in2 = get_in_reg(n, 3);
const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
- in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
- out = out ? out : in1;
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
+ in_name = "cl";
+ }
- snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", \
- arch_register_get_name(out), arch_register_get_name(in));
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
}
break;
case ia32_AddrModeS:
else {
const arch_register_t *in1 = get_in_reg(n, 2);
ir_mode *mode = get_ia32_res_mode(n);
+ const char *in_name;
+
+ mode = mode ? mode : get_ia32_ls_mode(n);
+ in_name = ia32_get_reg_name_for_mode(env, mode, in1);
- mode = mode ? mode : get_ia32_ls_mode(n);
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s",
- ia32_emit_am(n, env), ia32_get_reg_name_for_mode(env, mode, in1));
+ if (is_ia32_emit_cl(n)) {
+ assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
+ in_name = "cl";
+ }
+
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
}
break;
default:
return buf;
}
+/**
+ * Emits registers and/or address mode of a binary operation.
+ */
+char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+ static char *buf = NULL;
+
+ /* verify that this function is never called on non-AM supporting operations */
+ //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
+
+ if (! buf) {
+ buf = xcalloc(1, SNPRINTF_BUF_LEN);
+ }
+ else {
+ memset(buf, 0, SNPRINTF_BUF_LEN);
+ }
+
+ switch(get_ia32_op_type(n)) {
+ case ia32_Normal:
+ if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ }
+ else {
+ ia32_attr_t *attr = get_ia32_attr(n);
+ const arch_register_t *in1 = attr->x87[0];
+ const arch_register_t *in2 = attr->x87[1];
+ const arch_register_t *out = attr->x87[2];
+ const arch_register_t *in;
+ const char *in_name;
+
+ in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
+ out = out ? out : in1;
+ in_name = arch_register_get_name(in);
+
+ snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
+ }
+ break;
+ case ia32_AddrModeS:
+ case ia32_AddrModeD:
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+ break;
+ default:
+ assert(0 && "unsupported op type");
+ }
+
+#undef PRODUCES_RESULT
+
+ return buf;
+}
+
/**
* Emits registers and/or address mode of a unary operation.
*/
case 32:
obstack_printf(obst, "DWORD PTR ");
break;
+ case 64:
+ if (has_x87_register(n))
+ /* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
+ obstack_printf(obst, "QWORD PTR ");
+ break;
+ case 80:
+ case 96:
+ obstack_printf(obst, "XWORD PTR ");
+ break;
default:
break;
}
}
- obstack_printf(obst, "[");
+ /* emit address mode symconst */
+ if (get_ia32_am_sc(n)) {
+ if (is_ia32_am_sc_sign(n))
+ obstack_printf(obst, "-");
+ obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
+ }
if (am_flav & ia32_B) {
+ obstack_printf(obst, "[");
lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
had_output = 1;
}
if (had_output) {
obstack_printf(obst, "+");
}
+ else {
+ obstack_printf(obst, "[");
+ }
lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
if (am_flav & ia32_O) {
s = get_ia32_am_offs(n);
- /* omit explicit + if there was no base or index */
- if (! had_output && s[0] == '+')
- s++;
+ if (s) {
+ /* omit explicit + if there was no base or index */
+ if (! had_output) {
+ obstack_printf(obst, "[");
+ if (s[0] == '+')
+ s++;
+ }
- obstack_printf(obst, s);
+ obstack_printf(obst, s);
+ had_output = 1;
+ }
}
- obstack_printf(obst, "] ");
+ if (had_output)
+ obstack_printf(obst, "] ");
size = obstack_object_size(obst);
s = obstack_finish(obst);
{ NULL, pn_Cmp_False }, /* always false */
{ "e", pn_Cmp_Eq }, /* == */
{ "b", pn_Cmp_Lt }, /* < */
- { "be", pn_Cmp_Le }, /* <= */
+ { "be", pn_Cmp_Le }, /* <= */
{ "a", pn_Cmp_Gt }, /* > */
{ "ae", pn_Cmp_Ge }, /* >= */
{ "ne", pn_Cmp_Lg }, /* != */
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
IA32_DO_EMIT(irn);
- finish_CondJmp(F, irn, get_irn_mode(get_irn_n(irn, 2)));
+ finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
/**
CondJmp_emitter(irn, env);
}
-/**
- * Emits code for conditional jump with immediate.
- */
-static void emit_ia32_CondJmp_i(const ir_node *irn, ia32_emit_env_t *env) {
- CondJmp_emitter(irn, env);
-}
-
/**
* Emits code for conditional test and jump.
*/
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
IA32_DO_EMIT(irn);
- finish_CondJmp(F, irn, get_irn_mode(get_irn_n(irn, 0)));
+ finish_CondJmp(F, irn, get_ia32_res_mode(irn));
#undef IA32_IS_IMMOP
}
char cmnt_buf[SNPRINTF_BUF_LEN];
snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
- lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
IA32_DO_EMIT(irn);
- finish_CondJmp(F, irn, get_irn_mode(get_irn_n(irn, 0)));
+ finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
IA32_DO_EMIT(irn);
- finish_CondJmp(F, irn, get_irn_mode(get_irn_n(irn, 2)));
+ finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
/*********************************************************
* Emits code for an Int conversion.
*/
static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
- const lc_arg_env_t *env = ia32_get_arg_env();
- char *move_cmd, *conv_cmd;
+ FILE *F = emit_env->out;
+ const lc_arg_env_t *env = ia32_get_arg_env();
+ char *move_cmd = "movzx";
+ char *conv_cmd = NULL;
ir_mode *src_mode, *tgt_mode;
int n, m;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
else
assert(0 && "unsupported Conv_I2I");
}
- else {
- move_cmd = "movzx";
- conv_cmd = NULL;
- }
switch(get_ia32_op_type(irn)) {
case ia32_Normal:
FILE *F = emit_env->out;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
+ if (mode_is_float(get_irn_mode(irn)))
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
+ else
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
IA32_DO_EMIT(irn);
}
IA32_DO_EMIT(irn);
}
+
+
/***********************************************************************************
* _ __ _
* (_) / _| | |
* Emits code for a node.
*/
static void ia32_emit_node(const ir_node *irn, void *env) {
- ia32_emit_env_t *emit_env = env;
- firm_dbg_module_t *mod = emit_env->mod;
+ ia32_emit_env_t *emit_env = env;
FILE *F = emit_env->out;
ir_op *op = get_irn_op(irn);
+ DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
entity *irg_ent = get_irg_entity(irg);
const char *irg_name = get_entity_name(irg_ent);
- fprintf(F, "\t.text\n");
+ fprintf(F, "\t.section\t.text\n");
if (get_entity_visibility(irg_ent) == visibility_external_visible) {
fprintf(F, ".globl %s\n", irg_name);
}
ia32_emit_env_t emit_env;
ir_node *block;
- emit_env.mod = firm_dbg_register("firm.be.ia32.emitter");
emit_env.out = F;
emit_env.arch_env = cg->arch_env;
emit_env.cg = cg;
emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
+ FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
/* set the global arch_env (needed by print hooks) */
arch_env = cg->arch_env;
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