/* jump table for switch generation */
typedef struct _jmp_tbl_t {
- ir_node *defProj; /**< default target */
- long min_value; /**< smallest switch case */
- long max_value; /**< largest switch case */
- long num_branches; /**< number of jumps */
- char *label; /**< label of the jump table */
- branch_t *branches; /**< jump array */
+ ir_node *defProj; /**< default target */
+ long min_value; /**< smallest switch case */
+ long max_value; /**< largest switch case */
+ long num_branches; /**< number of jumps */
+ char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
+ branch_t *branches; /**< jump array */
} jmp_tbl_t;
/**
const ir_edge_t *edge;
/* fill the table structure */
- tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
- tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
+ get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
tbl.defProj = NULL;
tbl.num_branches = get_irn_n_edges(node) - 1;
tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
}
- if (tbl.label)
- free(tbl.label);
- if (tbl.branches)
- free(tbl.branches);
+ free(tbl.branches);
}
/**
be_emit_write_line();
}
-static void bemit16(const unsigned u16)
+static void bemit16(const unsigned short u16)
{
be_emit_irprintf("\t.word 0x%x\n", u16);
be_emit_write_line();
bemit8(modrm);
}
-/**
- * Calculate the size of an (unsigned) immediate in bytes.
- *
- * @param offset an offset
- */
-static unsigned get_unsigned_imm_size(unsigned offset)
-{
- if (offset < 256) {
- return 1;
- } else if (offset < 65536) {
- return 2;
- } else {
- return 4;
- }
-}
-
/**
* Calculate the size of an signed immediate in bytes.
*
*/
static void bemit_binop_2(const ir_node *node, unsigned code)
{
- const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
- ia32_op_type_t am_type = get_ia32_op_type(node);
- unsigned char d = 0;
- const arch_register_t *op2;
-
- switch (am_type) {
- case ia32_AddrModeS:
- d = 2;
- /* FALLTHROUGH */
- case ia32_AddrModeD:
- bemit8(code | d);
+ const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
+ bemit8(code);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
+ bemit_modrr(op2, out);
+ } else {
bemit_mod_am(reg_gp_map[out->index], node);
- return;
- case ia32_Normal:
- bemit8(code);
- op2 = get_in_reg(node, n_ia32_binary_right);
- bemit_modrr(out, op2);
- return;
}
- panic("invalid address mode");
}
/**
static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
{
- bemit8(code);
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
+ if (size == 16)
+ bemit8(0x66);
+ bemit8(size == 8 ? code : code + 1);
bemit_mod_am(ext, node);
}
panic("NIY");
} else {
assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
- bemit8(0x89);
- bemit_modrr(out, in);
+ bemit8(0x8B);
+ bemit_modrr(in, out);
}
}
}
/* insn def eax,imm imm */
-BINOP(add, 0x01, 0x05, 0x81, 0)
-BINOP(or, 0x09, 0x0D, 0x81, 1)
-BINOP(adc, 0x11, 0x15, 0x81, 2)
-BINOP(sbb, 0x19, 0x1D, 0x81, 3)
-BINOP(and, 0x21, 0x25, 0x81, 4)
-BINOP(sub, 0x29, 0x2D, 0x81, 5)
-BINOP(xor, 0x31, 0x35, 0x81, 6)
-BINOP(cmp, 0x39, 0x3D, 0x81, 7)
+BINOP(add, 0x03, 0x05, 0x81, 0)
+BINOP(or, 0x0B, 0x0D, 0x81, 1)
+BINOP(adc, 0x13, 0x15, 0x81, 2)
+BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
+BINOP(and, 0x23, 0x25, 0x81, 4)
+BINOP(sub, 0x2B, 0x2D, 0x81, 5)
+BINOP(xor, 0x33, 0x35, 0x81, 6)
BINOP(test, 0x85, 0xA9, 0xF7, 0)
+#define BINOPMEM(op, ext) \
+static void bemit_##op(const ir_node *node) \
+{ \
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
+ if (size == 16) \
+ bemit8(0x66); \
+ ir_node *val = get_irn_n(node, n_ia32_unary_op); \
+ if (is_ia32_Immediate(val)) { \
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
+ int offset = attr->offset; \
+ if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
+ bemit8(0x83); \
+ bemit_mod_am(ext, node); \
+ bemit8(offset); \
+ } else { \
+ bemit8(0x81); \
+ bemit_mod_am(ext, node); \
+ if (size == 16) { \
+ bemit16(offset); \
+ } else { \
+ bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
+ } \
+ } \
+ } else { \
+ bemit8(ext << 3 | 1); \
+ bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
+ } \
+} \
+ \
+static void bemit_##op##8bit(const ir_node *node) \
+{ \
+ ir_node *val = get_irn_n(node, n_ia32_unary_op); \
+ if (is_ia32_Immediate(val)) { \
+ bemit8(0x80); \
+ bemit_mod_am(ext, node); \
+ bemit8(get_ia32_immediate_attr_const(val)->offset); \
+ } else { \
+ bemit8(ext << 3); \
+ bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
+ } \
+}
+
+BINOPMEM(addmem, 0)
+BINOPMEM(ormem, 1)
+BINOPMEM(andmem, 4)
+BINOPMEM(submem, 5)
+BINOPMEM(xormem, 6)
+
+
/**
* Creates a function for an Unop with code /ext encoding.
*/
bemit8(0xD3); \
bemit_modru(out, ext); \
} \
+} \
+ \
+static void bemit_##op##mem(const ir_node *node) \
+{ \
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
+ if (size == 16) \
+ bemit8(0x66); \
+ ir_node *count = get_irn_n(node, 1); \
+ if (is_ia32_Immediate(count)) { \
+ int offset = get_ia32_immediate_attr_const(count)->offset; \
+ if (offset == 1) { \
+ bemit8(size == 1 ? 0xD0 : 0xD1); \
+ bemit_mod_am(ext, node); \
+ } else { \
+ bemit8(size == 1 ? 0xC0 : 0xC1); \
+ bemit_mod_am(ext, node); \
+ bemit8(offset); \
+ } \
+ } else { \
+ bemit8(size == 1 ? 0xD2 : 0xD3); \
+ bemit_mod_am(ext, node); \
+ } \
}
SHIFT(rol, 0)
SHIFT(shr, 5)
SHIFT(sar, 7)
+static void bemit_shld(const ir_node *node)
+{
+ const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
+ const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
+ ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
+ bemit8(0x0F);
+ if (is_ia32_Immediate(count)) {
+ bemit8(0xA4);
+ bemit_modrr(out, in);
+ bemit8(get_ia32_immediate_attr_const(count)->offset);
+ } else {
+ bemit8(0xA5);
+ bemit_modrr(out, in);
+ }
+}
+
+static void bemit_shrd(const ir_node *node)
+{
+ const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
+ const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
+ ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
+ bemit8(0x0F);
+ if (is_ia32_Immediate(count)) {
+ bemit8(0xAC);
+ bemit_modrr(out, in);
+ bemit8(get_ia32_immediate_attr_const(count)->offset);
+ } else {
+ bemit8(0xAD);
+ bemit_modrr(out, in);
+ }
+}
+
+static void bemit_cmov(const ir_node *node)
+{
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int ins_permuted = attr->data.ins_permuted;
+ const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
+ pn_Cmp pnc = get_ia32_condcode(node);
+ const arch_register_t *in_true;
+ const arch_register_t *in_false;
+
+ pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
+
+ in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
+ in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
+
+ /* should be same constraint fullfilled? */
+ if (out == in_false) {
+ /* yes -> nothing to do */
+ } else if (out == in_true) {
+ assert(get_ia32_op_type(node) == ia32_Normal);
+ ins_permuted = !ins_permuted;
+ in_true = in_false;
+ } else {
+ /* we need a mov */
+ bemit8(0x8B); // mov %in_false, %out
+ bemit_modrr(in_false, out);
+ }
+
+ if (ins_permuted)
+ pnc = ia32_get_negated_pnc(pnc);
+
+ /* TODO: handling of Nans isn't correct yet */
+
+ bemit8(0x0F);
+ bemit8(0x40 + pnc2cc(pnc));
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ bemit_modrr(in_true, out);
+ } else {
+ bemit_mod_am(reg_gp_map[out->index], node);
+ }
+}
+
+static void bemit_cmp(const ir_node *node)
+{
+ unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
+ ir_node *right;
+
+ if (ls_size == 16)
+ bemit8(0x66);
+
+ right = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(right)) {
+ /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
+ const ir_node *op = get_irn_n(node, n_ia32_binary_right);
+ const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
+ unsigned size;
+
+ if (attr->symconst != NULL) {
+ size = 4;
+ } else {
+ /* check for sign extension */
+ size = get_signed_imm_size(attr->offset);
+ }
+
+ switch (size) {
+ case 1:
+ bemit8(0x81 | SIGNEXT_IMM);
+ /* cmp has this special mode */
+ if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ bemit_mod_am(7, node);
+ } else {
+ const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ bemit_modru(reg, 7);
+ }
+ bemit8((unsigned char)attr->offset);
+ return;
+ case 2:
+ case 4:
+ /* check for eax variant: this variant is shorter for 32bit immediates only */
+ if (get_ia32_op_type(node) == ia32_AddrModeS) {
+ bemit8(0x81);
+ bemit_mod_am(7, node);
+ } else {
+ const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ if (reg->index == REG_EAX) {
+ bemit8(0x3D);
+ } else {
+ bemit8(0x81);
+ bemit_modru(reg, 7);
+ }
+ }
+ if (ls_size == 16) {
+ bemit16(attr->offset);
+ } else {
+ bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
+ }
+ return;
+ }
+ panic("invalid imm size?!?");
+ } else {
+ const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
+ bemit8(0x3B);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
+ bemit_modrr(op2, out);
+ } else {
+ bemit_mod_am(reg_gp_map[out->index], node);
+ }
+ }
+}
+
+static void bemit_cmp8bit(const ir_node *node)
+{
+ ir_node *right = get_irn_n(node, n_ia32_binary_right);
+ if (is_ia32_Immediate(right)) {
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
+ if (out->index == REG_EAX) {
+ bemit8(0x3C);
+ } else {
+ bemit8(0x80);
+ bemit_modru(out, 7);
+ }
+ } else {
+ bemit8(0x80);
+ bemit_mod_am(7, node);
+ }
+ bemit8(get_ia32_immediate_attr_const(right)->offset);
+ } else {
+ bemit8(0x3A);
+ const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
+ bemit_modrr(out, in);
+ } else {
+ bemit_mod_am(reg_gp_map[out->index], node);
+ }
+ }
+}
+
+static void bemit_test8bit(const ir_node *node)
+{
+ ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
+ if (is_ia32_Immediate(right)) {
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
+ if (out->index == REG_EAX) {
+ bemit8(0xA8);
+ } else {
+ bemit8(0xF6);
+ bemit_modru(out, 0);
+ }
+ } else {
+ bemit8(0xF6);
+ bemit_mod_am(0, node);
+ }
+ bemit8(get_ia32_immediate_attr_const(right)->offset);
+ } else {
+ bemit8(0x84);
+ const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
+ bemit_modrr(out, in);
+ } else {
+ bemit_mod_am(reg_gp_map[out->index], node);
+ }
+ }
+}
+
static void bemit_imul(const ir_node *node)
{
ir_node *right = get_irn_n(node, n_ia32_IMul_right);
bemit_unop_mem(node, code, ext); \
}
-UNOPMEM(notmem, 0xF7, 2)
-UNOPMEM(negmem, 0xF7, 3)
-UNOPMEM(incmem, 0xFF, 0)
-UNOPMEM(decmem, 0xFF, 1)
+UNOPMEM(notmem, 0xF6, 2)
+UNOPMEM(negmem, 0xF6, 3)
+UNOPMEM(incmem, 0xFE, 0)
+UNOPMEM(decmem, 0xFE, 1)
static void bemit_set(const ir_node *node)
{
bemit_modru(get_out_reg(node, pn_ia32_Set_res), 2);
}
+static void bemit_ldtls(const ir_node *node)
+{
+ const arch_register_t *out = get_out_reg(node, 0);
+
+ bemit8(0x65); // gs:
+ if (out->index == REG_EAX) {
+ bemit8(0xA1); // movl 0, %eax
+ } else {
+ bemit8(0x8B); // movl 0, %reg
+ bemit8(MOD_IND | ENC_REG(out->index) | ENC_RM(0x05));
+ }
+ bemit32(0);
+}
+
/**
* Emit a Lea.
*/
//EMIT_SINGLEOP(aaa, 0x37)
//EMIT_SINGLEOP(aas, 0x3F)
//EMIT_SINGLEOP(nop, 0x90)
-EMIT_SINGLEOP(cwtl, 0x98)
-EMIT_SINGLEOP(cltd, 0x99)
+EMIT_SINGLEOP(cwtl, 0x98)
+EMIT_SINGLEOP(cltd, 0x99)
//EMIT_SINGLEOP(fwait, 0x9B)
-EMIT_SINGLEOP(sahf, 0x9E)
+EMIT_SINGLEOP(sahf, 0x9E)
//EMIT_SINGLEOP(popf, 0x9D)
-EMIT_SINGLEOP(int3, 0xCC)
+EMIT_SINGLEOP(leave, 0xC9)
+EMIT_SINGLEOP(int3, 0xCC)
//EMIT_SINGLEOP(iret, 0xCF)
//EMIT_SINGLEOP(xlat, 0xD7)
//EMIT_SINGLEOP(lock, 0xF0)
-EMIT_SINGLEOP(rep, 0xF3)
+EMIT_SINGLEOP(rep, 0xF3)
//EMIT_SINGLEOP(halt, 0xF4)
-EMIT_SINGLEOP(cmc, 0xF5)
-EMIT_SINGLEOP(stc, 0xF9)
+EMIT_SINGLEOP(cmc, 0xF5)
+EMIT_SINGLEOP(stc, 0xF9)
//EMIT_SINGLEOP(cli, 0xFA)
//EMIT_SINGLEOP(sti, 0xFB)
//EMIT_SINGLEOP(std, 0xFD)
const arch_register_t *out = get_out_reg(node, 0);
if (out->index == REG_EAX) {
- ir_entity *ent = get_ia32_am_sc(node);
- int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
ir_node *index = get_irn_n(node, n_ia32_index);
int has_index = !is_ia32_NoReg_GP(index);
-
- if (ent == NULL && !has_base && !has_index) {
+ if (!has_base && !has_index) {
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
/* load from constant address to EAX can be encoded
as 0xA1 [offset] */
bemit8(0xA1);
- bemit_entity(NULL, 0, offs, false);
+ bemit_entity(ent, 0, offs, false);
return;
}
}
static void bemit_store(const ir_node *node)
{
const ir_node *value = get_irn_n(node, n_ia32_Store_val);
+ unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
if (is_ia32_Immediate(value)) {
- bemit8(0xC7);
- bemit_mod_am(0, node);
- bemit_immediate(value, false);
+ if (size == 8) {
+ bemit8(0xC6);
+ bemit_mod_am(0, node);
+ bemit8(get_ia32_immediate_attr_const(value)->offset);
+ } else if (size == 16) {
+ bemit8(0x66);
+ bemit8(0xC7);
+ bemit_mod_am(0, node);
+ bemit16(get_ia32_immediate_attr_const(value)->offset);
+ } else {
+ bemit8(0xC7);
+ bemit_mod_am(0, node);
+ bemit_immediate(value, false);
+ }
} else {
const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
if (in->index == REG_EAX) {
- ir_entity *ent = get_ia32_am_sc(node);
- int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
ir_node *index = get_irn_n(node, n_ia32_index);
int has_index = !is_ia32_NoReg_GP(index);
-
- if (ent == NULL && !has_base && !has_index) {
+ if (!has_base && !has_index) {
+ ir_entity *ent = get_ia32_am_sc(node);
+ int offs = get_ia32_am_offs_int(node);
/* store to constant address from EAX can be encoded as
- 0xA3 [offset]*/
- bemit8(0xA3);
- bemit_entity(NULL, 0, offs, false);
+ * 0xA2/0xA3 [offset]*/
+ if (size == 8) {
+ bemit8(0xA2);
+ } else {
+ if (size == 16)
+ bemit8(0x66);
+ bemit8(0xA3);
+ }
+ bemit_entity(ent, 0, offs, false);
return;
}
}
- bemit8(0x89);
+
+ if (size == 8) {
+ bemit8(0x88);
+ } else {
+ if (size == 16)
+ bemit8(0x66);
+ bemit8(0x89);
+ }
bemit_mod_am(reg_gp_map[in->index], node);
}
}
if (is_ia32_Immediate(value)) {
const ia32_immediate_attr_t *attr
= get_ia32_immediate_attr_const(value);
- unsigned size = get_unsigned_imm_size(attr->offset);
+ unsigned size = get_signed_imm_size(attr->offset);
if (attr->symconst)
size = 4;
switch (size) {
bemit_jmp_destination(dest_block);
}
+static void bemit_jp(bool odd, const ir_node *dest_block)
+{
+ bemit8(0x0F);
+ bemit8(0x8A + odd);
+ bemit_jmp_destination(dest_block);
+}
+
static void bemit_ia32_jcc(const ir_node *node)
{
int pnc = get_ia32_condcode(node);
- int need_parity_label = 0;
const ir_node *proj_true;
const ir_node *proj_false;
const ir_node *dest_true;
dest_false = get_cfop_target_block(proj_false);
if (pnc & ia32_pn_Cmp_float) {
- panic("Float jump NIY");
/* Some floating point comparisons require a test of the parity flag,
* which indicates that the result is unordered */
switch (pnc & 15) {
case pn_Cmp_Uo: {
- ia32_emitf(proj_true, "\tjp %L\n");
+ bemit_jp(false, dest_true);
break;
}
case pn_Cmp_Leg:
- ia32_emitf(proj_true, "\tjnp %L\n");
+ bemit_jp(true, dest_true);
break;
case pn_Cmp_Eq:
/* we need a local label if the false proj is a fallthrough
* as the falseblock might have no label emitted then */
if (can_be_fallthrough(proj_false)) {
- need_parity_label = 1;
- ia32_emitf(proj_false, "\tjp 1f\n");
+ bemit8(0x7A);
+ bemit8(0x06); // jp + 6
} else {
- ia32_emitf(proj_false, "\tjp %L\n");
+ bemit_jp(false, dest_false);
}
goto emit_jcc;
case pn_Cmp_Ug:
case pn_Cmp_Uge:
case pn_Cmp_Ne:
- ia32_emitf(proj_true, "\tjp %L\n");
+ bemit_jp(false, dest_true);
goto emit_jcc;
default:
bemit_jcc(pnc, dest_true);
}
- if (need_parity_label) {
- panic("parity label NIY");
- }
-
/* the second Proj might be a fallthrough */
if (can_be_fallthrough(proj_false)) {
/* it's a fallthrough */
}
}
+static void bemit_subsp(const ir_node *node)
+{
+ const arch_register_t *out;
+ /* sub %in, %esp */
+ bemit_sub(node);
+ /* mov %esp, %out */
+ bemit8(0x8B);
+ out = get_out_reg(node, 1);
+ bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
+}
+
static void bemit_incsp(const ir_node *node)
{
int offs;
}
}
+static void bemit_copybi(const ir_node *node)
+{
+ unsigned size = get_ia32_copyb_size(node);
+ if (size & 1)
+ bemit8(0xA4); // movsb
+ if (size & 2) {
+ bemit8(0x66);
+ bemit8(0xA5); // movsw
+ }
+ size >>= 2;
+ while (size--) {
+ bemit8(0xA5); // movsl
+ }
+}
+
+static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
+{
+ if (get_ia32_op_type(node) == ia32_Normal) {
+ const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
+ const arch_register_t *in1 = x87_attr->x87[0];
+ const arch_register_t *in = x87_attr->x87[1];
+ const arch_register_t *out = x87_attr->x87[2];
+
+ if (out == NULL) {
+ out = in1;
+ } else if (out == in) {
+ in = in1;
+ }
+
+ if (out->index == 0) {
+ bemit8(0xD8);
+ bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
+ } else {
+ bemit8(0xDC);
+ bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
+ }
+ } else {
+ if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
+ bemit8(0xD8);
+ } else {
+ bemit8(0xDC);
+ }
+ bemit_mod_am(code, node);
+ }
+}
+
+static void bemit_fbinopp(const ir_node *node, unsigned const code)
+{
+ const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
+ const arch_register_t *out = x87_attr->x87[2];
+ bemit8(0xDE);
+ bemit8(code + out->index);
+}
+
+static void bemit_fabs(const ir_node *node)
+{
+ (void)node;
+
+ bemit8(0xD9);
+ bemit8(0xE1);
+}
+
+static void bemit_fadd(const ir_node *node)
+{
+ bemit_fbinop(node, 0, 0);
+}
+
+static void bemit_faddp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xC0);
+}
+
+static void bemit_fchs(const ir_node *node)
+{
+ (void)node;
+
+ bemit8(0xD9);
+ bemit8(0xE0);
+}
+
+static void bemit_fdiv(const ir_node *node)
+{
+ bemit_fbinop(node, 6, 7);
+}
+
+static void bemit_fdivp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xF8);
+}
+
+static void bemit_fdivr(const ir_node *node)
+{
+ bemit_fbinop(node, 7, 6);
+}
+
+static void bemit_fdivrp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xF0);
+}
+
+static void bemit_fild(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 16:
+ bemit8(0xDF); // filds
+ bemit_mod_am(0, node);
+ return;
+
+ case 32:
+ bemit8(0xDB); // fildl
+ bemit_mod_am(0, node);
+ return;
+
+ case 64:
+ bemit8(0xDF); // fildll
+ bemit_mod_am(5, node);
+ return;
+
+ default:
+ panic("invalid mode size");
+ }
+}
+
+static void bemit_fist(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 16:
+ bemit8(0xDF); // fists
+ break;
+
+ case 32:
+ bemit8(0xDB); // fistl
+ break;
+
+ default:
+ panic("invalid mode size");
+ }
+ bemit_mod_am(2, node);
+}
+
+static void bemit_fistp(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 16:
+ bemit8(0xDF); // fistps
+ bemit_mod_am(3, node);
+ return;
+
+ case 32:
+ bemit8(0xDB); // fistpl
+ bemit_mod_am(3, node);
+ return;
+
+ case 64:
+ bemit8(0xDF); // fistpll
+ bemit_mod_am(7, node);
+ return;
+
+ default:
+ panic("invalid mode size");
+ }
+}
+
+static void bemit_fld(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 32:
+ bemit8(0xD9); // flds
+ bemit_mod_am(0, node);
+ return;
+
+ case 64:
+ bemit8(0xDD); // fldl
+ bemit_mod_am(0, node);
+ return;
+
+ case 80:
+ case 96:
+ bemit8(0xDB); // fldt
+ bemit_mod_am(5, node);
+ return;
+
+ default:
+ panic("invalid mode size");
+ }
+}
+
+static void bemit_fld1(const ir_node *node)
+{
+ (void)node;
+ bemit8(0xD9);
+ bemit8(0xE8); // fld1
+}
+
+static void bemit_fldcw(const ir_node *node)
+{
+ bemit8(0xD9); // fldcw
+ bemit_mod_am(5, node);
+}
+
+static void bemit_fldz(const ir_node *node)
+{
+ (void)node;
+ bemit8(0xD9);
+ bemit8(0xEE); // fldz
+}
+
+static void bemit_fmul(const ir_node *node)
+{
+ bemit_fbinop(node, 1, 1);
+}
+
+static void bemit_fmulp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xC8);
+}
+
+static void bemit_fpop(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xDD);
+ bemit8(0xD8 + attr->x87[0]->index);
+}
+
+static void bemit_fpush(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xD9);
+ bemit8(0xC0 + attr->x87[0]->index);
+}
+
+static void bemit_fpushcopy(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xD9);
+ bemit8(0xC0 + attr->x87[0]->index);
+}
+
+static void bemit_fst(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 32:
+ bemit8(0xD9); // fsts
+ break;
+
+ case 64:
+ bemit8(0xDD); // fstl
+ break;
+
+ default:
+ panic("invalid mode size");
+ }
+ bemit_mod_am(2, node);
+}
+
+static void bemit_fstp(const ir_node *node)
+{
+ switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
+ case 32:
+ bemit8(0xD9); // fstps
+ bemit_mod_am(3, node);
+ return;
+
+ case 64:
+ bemit8(0xDD); // fstpl
+ bemit_mod_am(3, node);
+ return;
+
+ case 80:
+ case 96:
+ bemit8(0xDB); // fstpt
+ bemit_mod_am(7, node);
+ return;
+
+ default:
+ panic("invalid mode size");
+ }
+}
+
+static void bemit_fsub(const ir_node *node)
+{
+ bemit_fbinop(node, 4, 5);
+}
+
+static void bemit_fsubp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xE8);
+}
+
+static void bemit_fsubr(const ir_node *node)
+{
+ bemit_fbinop(node, 5, 4);
+}
+
+static void bemit_fsubrp(const ir_node *node)
+{
+ bemit_fbinopp(node, 0xE0);
+}
+
+static void bemit_fnstcw(const ir_node *node)
+{
+ bemit8(0xD9); // fnstcw
+ bemit_mod_am(7, node);
+}
+
+static void bemit_fnstsw(void)
+{
+ bemit8(0xDF); // fnstsw %ax
+ bemit8(0xE0);
+}
+
+static void bemit_ftstfnstsw(const ir_node *node)
+{
+ (void)node;
+
+ bemit8(0xD9); // ftst
+ bemit8(0xE4);
+ bemit_fnstsw();
+}
+
+static void bemit_fucomi(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xDB); // fucomi
+ bemit8(0xE8 + attr->x87[1]->index);
+}
+
+static void bemit_fucomip(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xDF); // fucomip
+ bemit8(0xE8 + attr->x87[1]->index);
+}
+
+static void bemit_fucomfnstsw(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xDD); // fucom
+ bemit8(0xE0 + attr->x87[1]->index);
+ bemit_fnstsw();
+}
+
+static void bemit_fucompfnstsw(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xDD); // fucomp
+ bemit8(0xE8 + attr->x87[1]->index);
+ bemit_fnstsw();
+}
+
+static void bemit_fucomppfnstsw(const ir_node *node)
+{
+ (void)node;
+
+ bemit8(0xDA); // fucompp
+ bemit8(0xE9);
+ bemit_fnstsw();
+}
+
+static void bemit_fxch(const ir_node *node)
+{
+ const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
+ bemit8(0xD9);
+ bemit8(0xC8 + attr->x87[0]->index);
+}
+
/**
* The type of a emitter function.
*/
clear_irp_opcodes_generic_func();
/* benode emitter */
- register_emitter(op_be_Copy, bemit_copy);
- register_emitter(op_be_CopyKeep, bemit_copy);
- register_emitter(op_be_IncSP, bemit_incsp);
- register_emitter(op_be_Perm, bemit_perm);
- register_emitter(op_be_Return, bemit_return);
- register_emitter(op_ia32_Adc, bemit_adc);
- register_emitter(op_ia32_Add, bemit_add);
- register_emitter(op_ia32_And, bemit_and);
- register_emitter(op_ia32_Breakpoint, bemit_int3);
- register_emitter(op_ia32_Call, bemit_call);
- register_emitter(op_ia32_Cltd, bemit_cltd);
- register_emitter(op_ia32_Cmc, bemit_cmc);
- register_emitter(op_ia32_Cmp, bemit_cmp);
- register_emitter(op_ia32_Const, bemit_mov_const);
- register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
- register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
- register_emitter(op_ia32_Cwtl, bemit_cwtl);
- register_emitter(op_ia32_Dec, bemit_dec);
- register_emitter(op_ia32_DecMem, bemit_decmem);
- register_emitter(op_ia32_Div, bemit_div);
- register_emitter(op_ia32_IDiv, bemit_idiv);
- register_emitter(op_ia32_IJmp, bemit_ijmp);
- register_emitter(op_ia32_IMul1OP, bemit_imul1op);
- register_emitter(op_ia32_IMul, bemit_imul);
- register_emitter(op_ia32_Inc, bemit_inc);
- register_emitter(op_ia32_IncMem, bemit_incmem);
- register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
- register_emitter(op_ia32_Jmp, bemit_jump);
- register_emitter(op_ia32_Lea, bemit_lea);
- register_emitter(op_ia32_Load, bemit_load);
- register_emitter(op_ia32_Mul, bemit_mul);
- register_emitter(op_ia32_Neg, bemit_neg);
- register_emitter(op_ia32_NegMem, bemit_negmem);
- register_emitter(op_ia32_Not, bemit_not);
- register_emitter(op_ia32_NotMem, bemit_notmem);
- register_emitter(op_ia32_Or, bemit_or);
- register_emitter(op_ia32_Pop, bemit_pop);
- register_emitter(op_ia32_PopEbp, bemit_pop);
- register_emitter(op_ia32_PopMem, bemit_popmem);
- register_emitter(op_ia32_Push, bemit_push);
- register_emitter(op_ia32_RepPrefix, bemit_rep);
- register_emitter(op_ia32_Rol, bemit_rol);
- register_emitter(op_ia32_Ror, bemit_ror);
- register_emitter(op_ia32_Sahf, bemit_sahf);
- register_emitter(op_ia32_Sar, bemit_sar);
- register_emitter(op_ia32_Sbb, bemit_sbb);
- register_emitter(op_ia32_Set, bemit_set);
- register_emitter(op_ia32_Shl, bemit_shl);
- register_emitter(op_ia32_Shr, bemit_shr);
- register_emitter(op_ia32_Stc, bemit_stc);
- register_emitter(op_ia32_Store8Bit, bemit_store);
- register_emitter(op_ia32_Store, bemit_store);
- register_emitter(op_ia32_Sub, bemit_sub);
- register_emitter(op_ia32_Test, bemit_test);
- register_emitter(op_ia32_Xor0, bemit_xor0);
- register_emitter(op_ia32_Xor, bemit_xor);
+ register_emitter(op_be_Copy, bemit_copy);
+ register_emitter(op_be_CopyKeep, bemit_copy);
+ register_emitter(op_be_IncSP, bemit_incsp);
+ register_emitter(op_be_Perm, bemit_perm);
+ register_emitter(op_be_Return, bemit_return);
+ register_emitter(op_ia32_Adc, bemit_adc);
+ register_emitter(op_ia32_Add, bemit_add);
+ register_emitter(op_ia32_AddMem, bemit_addmem);
+ register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
+ register_emitter(op_ia32_And, bemit_and);
+ register_emitter(op_ia32_AndMem, bemit_andmem);
+ register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
+ register_emitter(op_ia32_Breakpoint, bemit_int3);
+ register_emitter(op_ia32_CMov, bemit_cmov);
+ register_emitter(op_ia32_Call, bemit_call);
+ register_emitter(op_ia32_Cltd, bemit_cltd);
+ register_emitter(op_ia32_Cmc, bemit_cmc);
+ register_emitter(op_ia32_Cmp, bemit_cmp);
+ register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
+ register_emitter(op_ia32_Const, bemit_mov_const);
+ register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
+ register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
+ register_emitter(op_ia32_CopyB_i, bemit_copybi);
+ register_emitter(op_ia32_Cwtl, bemit_cwtl);
+ register_emitter(op_ia32_Dec, bemit_dec);
+ register_emitter(op_ia32_DecMem, bemit_decmem);
+ register_emitter(op_ia32_Div, bemit_div);
+ register_emitter(op_ia32_FldCW, bemit_fldcw);
+ register_emitter(op_ia32_FnstCW, bemit_fnstcw);
+ register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
+ register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
+ register_emitter(op_ia32_Fucomi, bemit_fucomi);
+ register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
+ register_emitter(op_ia32_Fucompi, bemit_fucomip);
+ register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
+ register_emitter(op_ia32_IDiv, bemit_idiv);
+ register_emitter(op_ia32_IJmp, bemit_ijmp);
+ register_emitter(op_ia32_IMul, bemit_imul);
+ register_emitter(op_ia32_IMul1OP, bemit_imul1op);
+ register_emitter(op_ia32_Inc, bemit_inc);
+ register_emitter(op_ia32_IncMem, bemit_incmem);
+ register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
+ register_emitter(op_ia32_Jmp, bemit_jump);
+ register_emitter(op_ia32_LdTls, bemit_ldtls);
+ register_emitter(op_ia32_Lea, bemit_lea);
+ register_emitter(op_ia32_Leave, bemit_leave);
+ register_emitter(op_ia32_Load, bemit_load);
+ register_emitter(op_ia32_Mul, bemit_mul);
+ register_emitter(op_ia32_Neg, bemit_neg);
+ register_emitter(op_ia32_NegMem, bemit_negmem);
+ register_emitter(op_ia32_Not, bemit_not);
+ register_emitter(op_ia32_NotMem, bemit_notmem);
+ register_emitter(op_ia32_Or, bemit_or);
+ register_emitter(op_ia32_OrMem, bemit_ormem);
+ register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
+ register_emitter(op_ia32_Pop, bemit_pop);
+ register_emitter(op_ia32_PopEbp, bemit_pop);
+ register_emitter(op_ia32_PopMem, bemit_popmem);
+ register_emitter(op_ia32_Push, bemit_push);
+ register_emitter(op_ia32_RepPrefix, bemit_rep);
+ register_emitter(op_ia32_Rol, bemit_rol);
+ register_emitter(op_ia32_RolMem, bemit_rolmem);
+ register_emitter(op_ia32_Ror, bemit_ror);
+ register_emitter(op_ia32_RorMem, bemit_rormem);
+ register_emitter(op_ia32_Sahf, bemit_sahf);
+ register_emitter(op_ia32_Sar, bemit_sar);
+ register_emitter(op_ia32_SarMem, bemit_sarmem);
+ register_emitter(op_ia32_Sbb, bemit_sbb);
+ register_emitter(op_ia32_Set, bemit_set);
+ register_emitter(op_ia32_Shl, bemit_shl);
+ register_emitter(op_ia32_ShlD, bemit_shld);
+ register_emitter(op_ia32_ShlMem, bemit_shlmem);
+ register_emitter(op_ia32_Shr, bemit_shr);
+ register_emitter(op_ia32_ShrD, bemit_shrd);
+ register_emitter(op_ia32_ShrMem, bemit_shrmem);
+ register_emitter(op_ia32_Stc, bemit_stc);
+ register_emitter(op_ia32_Store, bemit_store);
+ register_emitter(op_ia32_Store8Bit, bemit_store);
+ register_emitter(op_ia32_Sub, bemit_sub);
+ register_emitter(op_ia32_SubMem, bemit_submem);
+ register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
+ register_emitter(op_ia32_SubSP, bemit_subsp);
+ register_emitter(op_ia32_Test, bemit_test);
+ register_emitter(op_ia32_Test8Bit, bemit_test8bit);
+ register_emitter(op_ia32_Xor, bemit_xor);
+ register_emitter(op_ia32_Xor0, bemit_xor0);
+ register_emitter(op_ia32_XorMem, bemit_xormem);
+ register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
+ register_emitter(op_ia32_fabs, bemit_fabs);
+ register_emitter(op_ia32_fadd, bemit_fadd);
+ register_emitter(op_ia32_faddp, bemit_faddp);
+ register_emitter(op_ia32_fchs, bemit_fchs);
+ register_emitter(op_ia32_fdiv, bemit_fdiv);
+ register_emitter(op_ia32_fdivp, bemit_fdivp);
+ register_emitter(op_ia32_fdivr, bemit_fdivr);
+ register_emitter(op_ia32_fdivrp, bemit_fdivrp);
+ register_emitter(op_ia32_fild, bemit_fild);
+ register_emitter(op_ia32_fist, bemit_fist);
+ register_emitter(op_ia32_fistp, bemit_fistp);
+ register_emitter(op_ia32_fld, bemit_fld);
+ register_emitter(op_ia32_fld1, bemit_fld1);
+ register_emitter(op_ia32_fldz, bemit_fldz);
+ register_emitter(op_ia32_fmul, bemit_fmul);
+ register_emitter(op_ia32_fmulp, bemit_fmulp);
+ register_emitter(op_ia32_fpop, bemit_fpop);
+ register_emitter(op_ia32_fpush, bemit_fpush);
+ register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
+ register_emitter(op_ia32_fst, bemit_fst);
+ register_emitter(op_ia32_fstp, bemit_fstp);
+ register_emitter(op_ia32_fsub, bemit_fsub);
+ register_emitter(op_ia32_fsubp, bemit_fsubp);
+ register_emitter(op_ia32_fsubr, bemit_fsubr);
+ register_emitter(op_ia32_fsubrp, bemit_fsubrp);
+ register_emitter(op_ia32_fxch, bemit_fxch);
/* ignore the following nodes */
register_emitter(op_ia32_ProduceVal, emit_Nothing);
projects / libfirm / blobdiff