* |_| |_|
*************************************************************/
+static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
+ return \
+ REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
+}
+
/**
* returns true if a node has x87 registers
*/
-static int has_x87_register(const ir_node *n) {
+static INLINE int has_x87_register(const ir_node *n) {
return is_irn_machine_user(n, 0);
}
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- buf = get_ia32_reg_name(X, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
+ buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
/* append the stupid % to register names */
lc_appendable_chadd(app, '%');
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
ia32_attr_t *attr;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- attr = get_ia32_attr(X);
+ attr = get_ia32_attr(irn);
buf = attr->x87[nr]->name;
lc_appendable_chadd(app, '%');
return lc_appendable_snadd(app, buf, strlen(buf));
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (occ->conversion == 'C') {
- buf = get_ia32_cnst(X);
+ buf = get_ia32_cnst(irn);
}
else { /* 'O' */
- buf = get_ia32_am_offs(X);
+ buf = get_ia32_am_offs(irn);
}
return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
static int ia32_get_mode_suffix(lc_appendable_t *app,
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
- ir_node *X = arg->v_ptr;
- ir_mode *mode = get_irn_mode(X);
+ ir_node *irn = arg->v_ptr;
+ ir_mode *mode = get_irn_mode(irn);
if (mode == mode_T) {
- mode = (is_ia32_Ld(X) || is_ia32_St(X)) ? get_ia32_ls_mode(X) : get_ia32_res_mode(X);
+ mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn);
}
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (mode_is_float(mode)) {
return env;
}
-static char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
+static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
switch(get_mode_size_bits(mode)) {
case 8:
return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
return buf;
}
+/**
+ * Returns the xxx PTR string for a given mode
+ *
+ * @param mode the mode
+ * @param x87_insn if non-zero returns the string for a x87 instruction
+ * else for a SSE instruction
+ */
+static const char *pointer_size(ir_mode *mode, int x87_insn)
+{
+ if (mode) {
+ switch (get_mode_size_bits(mode)) {
+ case 8: return "BYTE PTR";
+ case 16: return "WORD PTR";
+ case 32: return "DWORD PTR";
+ case 64:
+ if (x87_insn)
+ return "QWORD PTR";
+ return NULL;
+ case 80:
+ case 96: return "XWORD PTR";
+ default: return NULL;
+ }
+ }
+ return NULL;
+}
+
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
switch(get_ia32_op_type(n)) {
case ia32_Normal:
if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ ir_mode *mode = get_ia32_ls_mode(n);
+ const char *p = pointer_size(mode, 1);
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
}
else {
ia32_attr_t *attr = get_ia32_attr(n);
/**
* Emits registers and/or address mode of a unary operation.
*/
-char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
if (! buf) {
/**
* Emits address mode.
*/
-char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
int had_output = 0;
- char *s;
+ char *s;
+ const char *p;
int size;
static struct obstack *obst = NULL;
ir_mode *mode = get_ia32_ls_mode(n);
/* obstack_free with NULL results in an uninitialized obstack */
obstack_init(obst);
- if (mode) {
- switch (get_mode_size_bits(mode)) {
- case 8:
- obstack_printf(obst, "BYTE PTR ");
- break;
- case 16:
- obstack_printf(obst, "WORD PTR ");
- break;
- case 32:
- obstack_printf(obst, "DWORD PTR ");
- break;
- case 64:
- if (has_x87_register(n))
- /* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
- obstack_printf(obst, "QWORD PTR ");
- break;
- case 80:
- case 96:
- obstack_printf(obst, "XWORD PTR ");
- break;
- default:
- break;
- }
- }
+ p = pointer_size(mode, has_x87_register(n));
+ if (p)
+ obstack_printf(obst, "%s ", p);
/* emit address mode symconst */
if (get_ia32_am_sc(n)) {
return s;
}
+/**
+ * emit an address
+ */
+const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
+{
+ static char buf[SNPRINTF_BUF_LEN];
+ ir_mode *mode = get_ia32_ls_mode(irn);
+ const char *adr = get_ia32_cnst(irn);
+ const char *pref = pointer_size(mode, has_x87_register(irn));
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
+ return buf;
+}
/**
* Formated print of commands and comments.
finish_CondJmp(F, irn, mode_Is);
}
+static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2, *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2));
+ in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3));
+
+ /* we have to emit the cmp first, because the destination register */
+ /* could be one of the compare registers */
+ if (is_ia32_CMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else {
+ assert(0 && "unsupported CMov");
+ }
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ if (REGS_ARE_EQUAL(out, in2)) {
+ /* best case: default in == out -> do nothing */
+ }
+ else if (REGS_ARE_EQUAL(out, in1)) {
+ /* true in == out -> need complement compare and exchange true and default in */
+ ir_node *t = get_irn_n(irn, 2);
+ set_irn_n(irn, 2, get_irn_n(irn, 3));
+ set_irn_n(irn, 3, t);
+
+ cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+
+ }
+ else {
+ /* out is different from in: need copy default -> out */
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
+ IA32_DO_EMIT(irn);
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void Set_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+ const char *instr = "xor";
+ const char *reg8bit;
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
+
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ instr = "sub";
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %1D", instr, irn, irn);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+ IA32_DO_EMIT(irn);
+
+ if (is_ia32_Set(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else {
+ assert(0 && "unsupported Set");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_Set(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, env);
+}
+
+static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int sse_pnc = -1;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ switch (get_ia32_pncode(irn)) {
+ case pn_Cmp_Leg: /* odered */
+ sse_pnc = 7;
+ break;
+ case pn_Cmp_Uo: /* unordered */
+ sse_pnc = 3;
+ break;
+ case pn_Cmp_Ue: /* == */
+ sse_pnc = 0;
+ break;
+ case pn_Cmp_Ul: /* < */
+ sse_pnc = 1;
+ break;
+ case pn_Cmp_Ule: /* <= */
+ sse_pnc = 2;
+ break;
+ case pn_Cmp_Ug: /* > */
+ sse_pnc = 6;
+ break;
+ case pn_Cmp_Uge: /* >= */
+ sse_pnc = 5;
+ break;
+ case pn_Cmp_Ne: /* != */
+ sse_pnc = 4;
+ break;
+ }
+
+ assert(sse_pnc >= 0 && "unsupported floating point compare");
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
+ IA32_DO_EMIT(irn);
+}
+
/*********************************************************
* _ _ _
* (_) | (_)
const arch_env_t *aenv = emit_env->arch_env;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))))
+ if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))) ||
+ be_is_unknown_reg(arch_get_irn_register(aenv, be_get_Copy_op(irn))))
return;
if (mode_is_float(get_irn_mode(irn)))
lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
}
+static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
+}
+
/***********************************************************************************
IA32_EMIT(TestJmp);
IA32_EMIT(CJmp);
IA32_EMIT(CJmpAM);
+ IA32_EMIT(CMov);
+ IA32_EMIT(Set);
IA32_EMIT(SwitchJmp);
IA32_EMIT(CopyB);
IA32_EMIT(CopyB_i);
IA32_EMIT(Conv_I2I);
IA32_EMIT(Conv_I2I8Bit);
IA32_EMIT(Const);
+ IA32_EMIT(xCmp);
+ IA32_EMIT(xCmpSet);
+ IA32_EMIT(xCmpCMov);
IA32_EMIT2(fcomJmp, x87CondJmp);
IA32_EMIT2(fcompJmp, x87CondJmp);
IA32_EMIT2(fcomppJmp, x87CondJmp);
BE_EMIT(SetSP);
BE_EMIT(Copy);
BE_EMIT(Perm);
+ BE_EMIT(Return);
/* firm emitter */
EMIT(Jmp);
static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
- fprintf(F, "\tret\n");
ia32_dump_function_size(F, irg_name);
fprintf(F, "\n");
}
projects / libfirm / blobdiff