#include "ia32_nodes_attr.h"
#include "ia32_new_nodes.h"
#include "ia32_map_regs.h"
+#include "bearch_ia32_t.h"
#define BLOCK_PREFIX(x) ".L" x
/* global arch_env for lc_printf functions */
static const arch_env_t *arch_env = NULL;
+/** by default, we generate assembler code for the Linux gas */
+asm_flavour_t asm_flavour = ASM_LINUX_GAS;
+
+/**
+ * Switch to a new section
+ */
+void ia32_switch_section(FILE *F, section_t sec) {
+ static section_t curr_sec = NO_SECTION;
+ static const char *text[ASM_MAX][SECTION_MAX] = {
+ {
+ ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
+ },
+ {
+ ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
+ }
+ };
+
+ if (curr_sec == sec)
+ return;
+
+ curr_sec = sec;
+ switch (sec) {
+
+ case NO_SECTION:
+ break;
+
+ case SECTION_TEXT:
+ case SECTION_DATA:
+ case SECTION_RODATA:
+ case SECTION_COMMON:
+ fprintf(F, "\t%s\n", text[asm_flavour][sec]);
+ }
+}
+
+static void ia32_dump_function_object(FILE *F, const char *name)
+{
+ switch (asm_flavour) {
+ case ASM_LINUX_GAS:
+ fprintf(F, "\t.type\t%s, @function\n", name);
+ break;
+ case ASM_MINGW_GAS:
+ fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
+ break;
+ }
+}
+
+static void ia32_dump_function_size(FILE *F, const char *name)
+{
+ switch (asm_flavour) {
+ case ASM_LINUX_GAS:
+ fprintf(F, "\t.size\t%s, .-%s\n", name, name);
+ break;
+ }
+}
+
/*************************************************************
* _ _ __ _ _
* (_) | | / _| | | | |
* |_| |_|
*************************************************************/
+static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
+ return \
+ REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
+ REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
+}
+
/**
* returns true if a node has x87 registers
*/
-static int has_x87_register(const ir_node *n) {
+static INLINE int has_x87_register(const ir_node *n) {
return is_irn_machine_user(n, 0);
}
reg = arch_get_irn_register(arch_env, op);
assert(reg && "no in register found");
+
+ /* in case of unknown: just return a register */
+ if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
+ reg = &ia32_gp_regs[REG_EAX];
+ else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
+ reg = &ia32_xmm_regs[REG_XMM0];
+ else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
+ reg = &ia32_vfp_regs[REG_VF0];
+
return reg;
}
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- buf = get_ia32_reg_name(X, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
+ buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
/* append the stupid % to register names */
lc_appendable_chadd(app, '%');
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
int nr = occ->width - 1;
ia32_attr_t *attr;
- if (!X)
+ if (! irn)
return lc_appendable_snadd(app, "(null)", 6);
- attr = get_ia32_attr(X);
+ attr = get_ia32_attr(irn);
buf = attr->x87[nr]->name;
lc_appendable_chadd(app, '%');
return lc_appendable_snadd(app, buf, strlen(buf));
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
const char *buf;
- ir_node *X = arg->v_ptr;
+ ir_node *irn = arg->v_ptr;
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (occ->conversion == 'C') {
- buf = get_ia32_cnst(X);
+ buf = get_ia32_cnst(irn);
}
else { /* 'O' */
- buf = get_ia32_am_offs(X);
+ buf = get_ia32_am_offs(irn);
}
return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
static int ia32_get_mode_suffix(lc_appendable_t *app,
const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
{
- ir_node *X = arg->v_ptr;
- ir_mode *mode = get_irn_mode(X);
+ ir_node *irn = arg->v_ptr;
+ ir_mode *mode = get_irn_mode(irn);
if (mode == mode_T) {
- mode = is_ia32_AddrModeS(X) || is_ia32_AddrModeD(X) ? get_ia32_ls_mode(X) : get_ia32_res_mode(X);
+ mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn);
}
- if (!X)
+ if (! irn)
return lc_arg_append(app, occ, "(null)", 6);
if (mode_is_float(mode)) {
return env;
}
-static char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
+static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
switch(get_mode_size_bits(mode)) {
case 8:
return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
(!(is_ia32_St(n) || \
is_ia32_Store8Bit(n) || \
is_ia32_CondJmp(n) || \
- is_ia32_fCondJmp(n) || \
+ is_ia32_xCondJmp(n) || \
is_ia32_SwitchJmp(n)))
if (! buf) {
snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
}
else {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S, %s", n, ia32_emit_am(n, env));
+ if (PRODUCES_RESULT(n)) {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
+ }
+ else {
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
+ }
}
break;
case ia32_AddrModeD:
return buf;
}
+/**
+ * Returns the xxx PTR string for a given mode
+ *
+ * @param mode the mode
+ * @param x87_insn if non-zero returns the string for a x87 instruction
+ * else for a SSE instruction
+ */
+static const char *pointer_size(ir_mode *mode, int x87_insn)
+{
+ if (mode) {
+ switch (get_mode_size_bits(mode)) {
+ case 8: return "BYTE PTR";
+ case 16: return "WORD PTR";
+ case 32: return "DWORD PTR";
+ case 64:
+ if (x87_insn)
+ return "QWORD PTR";
+ return NULL;
+ case 80:
+ case 96: return "XWORD PTR";
+ default: return NULL;
+ }
+ }
+ return NULL;
+}
+
/**
* Emits registers and/or address mode of a binary operation.
*/
-char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
/* verify that this function is never called on non-AM supporting operations */
switch(get_ia32_op_type(n)) {
case ia32_Normal:
if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
- lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+ ir_mode *mode = get_ia32_ls_mode(n);
+ const char *p = pointer_size(mode, 1);
+ lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
}
else {
ia32_attr_t *attr = get_ia32_attr(n);
/**
* Emits registers and/or address mode of a unary operation.
*/
-char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
static char *buf = NULL;
if (! buf) {
lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
}
break;
- case ia32_am_Dest:
- snprintf(buf, SNPRINTF_BUF_LEN, ia32_emit_am(n, env));
+ case ia32_AddrModeD:
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
break;
default:
assert(0 && "unsupported op type");
/**
* Emits address mode.
*/
-char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
int had_output = 0;
- char *s;
+ char *s;
+ const char *p;
int size;
static struct obstack *obst = NULL;
ir_mode *mode = get_ia32_ls_mode(n);
/* obstack_free with NULL results in an uninitialized obstack */
obstack_init(obst);
- if (mode) {
- switch (get_mode_size_bits(mode)) {
- case 8:
- obstack_printf(obst, "BYTE PTR ");
- break;
- case 16:
- obstack_printf(obst, "WORD PTR ");
- break;
- case 32:
- obstack_printf(obst, "DWORD PTR ");
- break;
- case 64:
- if (has_x87_register(n))
- /* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
- obstack_printf(obst, "QWORD PTR ");
- break;
- case 80:
- case 96:
- obstack_printf(obst, "XWORD PTR ");
- break;
- default:
- break;
- }
- }
+ p = pointer_size(mode, has_x87_register(n));
+ if (p)
+ obstack_printf(obst, "%s ", p);
/* emit address mode symconst */
if (get_ia32_am_sc(n)) {
return s;
}
+/**
+ * emit an address
+ */
+const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
+{
+ static char buf[SNPRINTF_BUF_LEN];
+ ir_mode *mode = get_ia32_ls_mode(irn);
+ const char *adr = get_ia32_cnst(irn);
+ const char *pref = pointer_size(mode, has_x87_register(irn));
+ snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
+ return buf;
+}
/**
* Formated print of commands and comments.
return get_irn_link(block);
}
+/**
+ * Returns the Proj with projection number proj and NOT mode_M
+ */
+static ir_node *get_proj(const ir_node *irn, long proj) {
+ const ir_edge_t *edge;
+ ir_node *src;
+
+ assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
+
+ foreach_out_edge(irn, edge) {
+ src = get_edge_src_irn(edge);
+
+ assert(is_Proj(src) && "Proj expected");
+ if (get_irn_mode(src) == mode_M)
+ continue;
+
+ if (get_Proj_proj(src) == proj)
+ return src;
+ }
+ return NULL;
+}
+
/**
* Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
*/
static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
const ir_node *proj1, *proj2 = NULL;
const ir_node *block, *next_bl = NULL;
- const ir_edge_t *edge;
char buf[SNPRINTF_BUF_LEN];
char cmd_buf[SNPRINTF_BUF_LEN];
char cmnt_buf[SNPRINTF_BUF_LEN];
/* get both Proj's */
- edge = get_irn_out_edge_first(irn);
- proj1 = get_edge_src_irn(edge);
- assert(is_Proj(proj1) && "CondJmp with a non-Proj");
+ proj1 = get_proj(irn, pn_Cond_true);
+ assert(proj1 && "CondJmp without true Proj");
- edge = get_irn_out_edge_next(irn, edge);
- if (edge) {
- proj2 = get_edge_src_irn(edge);
- assert(is_Proj(proj2) && "CondJmp with a non-Proj");
- }
+ proj2 = get_proj(irn, pn_Cond_false);
+ assert(proj2 && "CondJmp without false Proj");
/* for now, the code works for scheduled and non-schedules blocks */
block = get_nodes_block(irn);
- if (proj2) {
- /* we have a block schedule */
- next_bl = next_blk_sched(block);
-
- if (get_cfop_target_block(proj1) == next_bl) {
- /* exchange both proj's so the second one can be omitted */
- const ir_node *t = proj1;
- proj1 = proj2;
- proj2 = t;
- }
+
+ /* we have a block schedule */
+ next_bl = next_blk_sched(block);
+
+ if (get_cfop_target_block(proj1) == next_bl) {
+ /* exchange both proj's so the second one can be omitted */
+ const ir_node *t = proj1;
+ proj1 = proj2;
+ proj2 = t;
}
/* the first Proj must always be created */
IA32_DO_EMIT(irn);
/* the second Proj might be a fallthrough */
- if (proj2) {
- if (get_cfop_target_block(proj2) != next_bl) {
- snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
- }
- else {
- cmd_buf[0] = '\0';
- snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrogh %s */", get_cfop_target(proj2, buf));
- }
- IA32_DO_EMIT(irn);
+ if (get_cfop_target_block(proj2) != next_bl) {
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
+ }
+ else {
+ cmd_buf[0] = '\0';
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
}
+ IA32_DO_EMIT(irn);
}
/**
finish_CondJmp(F, irn, get_ia32_res_mode(irn));
}
+/**
+ * Emits code for conditional x87 floating point jump with two variables.
+ */
+static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ ia32_attr_t *attr = get_ia32_attr(irn);
+ const char *reg = attr->x87[1]->name;
+ const char *instr = "fcom";
+ int reverse = 0;
+
+ switch (get_ia32_pncode(irn)) {
+ case iro_ia32_fcomrJmp:
+ reverse = 1;
+ case iro_ia32_fcomJmp:
+ default:
+ instr = "fucom";
+ break;
+ case iro_ia32_fcomrpJmp:
+ reverse = 1;
+ case iro_ia32_fcompJmp:
+ instr = "fucomp";
+ break;
+ case iro_ia32_fcomrppJmp:
+ reverse = 1;
+ case iro_ia32_fcomppJmp:
+ instr = "fucompp";
+ reg = "";
+ break;
+ }
+
+ if (reverse)
+ set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s", instr, reg);
+ lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+ IA32_DO_EMIT(irn);
+// lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %3D", irn);
+ lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
+ IA32_DO_EMIT(irn);
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
+ IA32_DO_EMIT(irn);
+
+ finish_CondJmp(F, irn, mode_Is);
+}
+
+static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *in1, *in2, *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2));
+ in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3));
+
+ /* we have to emit the cmp first, because the destination register */
+ /* could be one of the compare registers */
+ if (is_ia32_CMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpCMov(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else {
+ assert(0 && "unsupported CMov");
+ }
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ if (REGS_ARE_EQUAL(out, in2)) {
+ /* best case: default in == out -> do nothing */
+ }
+ else if (REGS_ARE_EQUAL(out, in1)) {
+ /* true in == out -> need complement compare and exchange true and default in */
+ ir_node *t = get_irn_n(irn, 2);
+ set_irn_n(irn, 2, get_irn_n(irn, 3));
+ set_irn_n(irn, 3, t);
+
+ cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+
+ }
+ else {
+ /* out is different from in: need copy default -> out */
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
+ IA32_DO_EMIT(irn);
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+ CMov_emitter(irn, env);
+}
+
+static void Set_emitter(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
+ const char *instr = "xor";
+ const char *reg8bit;
+
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+ const arch_register_t *out;
+
+ out = arch_get_irn_register(env->arch_env, irn);
+ reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
+
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ instr = "sub";
+ }
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %1D", instr, irn, irn);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+ IA32_DO_EMIT(irn);
+
+ if (is_ia32_Set(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+ }
+ else if (is_ia32_xCmpSet(irn)) {
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+ }
+ else {
+ assert(0 && "unsupported Set");
+ }
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
+ IA32_DO_EMIT(irn);
+
+ snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
+ snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
+ IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_Set(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
+ Set_emitter(irn, env);
+}
+
+static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+ int sse_pnc = -1;
+ char cmd_buf[SNPRINTF_BUF_LEN];
+ char cmnt_buf[SNPRINTF_BUF_LEN];
+
+ switch (get_ia32_pncode(irn)) {
+ case pn_Cmp_Leg: /* odered */
+ sse_pnc = 7;
+ break;
+ case pn_Cmp_Uo: /* unordered */
+ sse_pnc = 3;
+ break;
+ case pn_Cmp_Ue: /* == */
+ sse_pnc = 0;
+ break;
+ case pn_Cmp_Ul: /* < */
+ sse_pnc = 1;
+ break;
+ case pn_Cmp_Ule: /* <= */
+ sse_pnc = 2;
+ break;
+ case pn_Cmp_Ug: /* > */
+ sse_pnc = 6;
+ break;
+ case pn_Cmp_Uge: /* >= */
+ sse_pnc = 5;
+ break;
+ case pn_Cmp_Ne: /* != */
+ sse_pnc = 4;
+ break;
+ }
+
+ assert(sse_pnc >= 0 && "unsupported floating point compare");
+
+ lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
+ lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
+ IA32_DO_EMIT(irn);
+}
+
/*********************************************************
* _ _ _
* (_) | (_)
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
IA32_DO_EMIT(irn);
- fprintf(F, "\t.section\t.rodata\n");
+ ia32_switch_section(F, SECTION_RODATA);
fprintf(F, "\t.align 4\n");
fprintf(F, "%s:\n", tbl.label);
snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
IA32_DO_EMIT(irn);
}
-
- fprintf(F, "\n\t.text\n\n");
+ ia32_switch_section(F, SECTION_TEXT);
}
else {
/* one jump is enough */
* Emit rep movsd instruction for memcopy.
*/
static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
- FILE *F = emit_env->out;
- tarval *tv = get_ia32_Immop_tarval(irn);
- int rem = get_tarval_long(tv);
- int size = get_tarval_long(get_ia32_Immop_tarval(get_irn_n(irn, 2)));
+ FILE *F = emit_env->out;
+ tarval *tv = get_ia32_Immop_tarval(irn);
+ int rem = get_tarval_long(tv);
+ ir_node *size_node = get_irn_n(irn, 2);
+ int size;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+ /* beware: size_node could be a be_Copy to fulfill constraints for ecx */
+ size_node = be_is_Copy(size_node) ? be_get_Copy_op(size_node) : size_node;
+ size = get_tarval_long(get_ia32_Immop_tarval(size_node));
+
emit_CopyB_prolog(F, rem, size);
snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
const arch_env_t *aenv = emit_env->arch_env;
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
- if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))))
+ if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))) ||
+ be_is_unknown_reg(arch_get_irn_register(aenv, be_get_Copy_op(irn))))
return;
if (mode_is_float(get_irn_mode(irn)))
IA32_DO_EMIT(irn);
}
+/**
+ * Emits code for Constant loading.
+ */
+static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ char cmd_buf[256], cmnt_buf[256];
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+ if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
+ const char *instr = "xor";
+ if (env->isa->opt_arch == arch_pentium_4) {
+ /* P4 prefers sub r, r, others xor r, r */
+ instr = "sub";
+ }
+ lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+ }
+ else {
+ if (get_ia32_op_type(n) == ia32_SymConst) {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+ }
+ else {
+ lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
+ lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
+ }
+ }
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+}
+
+static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
+ FILE *F = env->out;
+ const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+ lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
+}
+
/***********************************************************************************
*/
static void ia32_register_emitters(void) {
-#define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
-#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
-#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
+#define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
+#define IA32_EMIT(a) IA32_EMIT2(a,a)
+#define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
+#define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
/* first clear the generic function pointer for all ops */
clear_irp_opcodes_generic_func();
IA32_EMIT(TestJmp);
IA32_EMIT(CJmp);
IA32_EMIT(CJmpAM);
+ IA32_EMIT(CMov);
+ IA32_EMIT(Set);
IA32_EMIT(SwitchJmp);
IA32_EMIT(CopyB);
IA32_EMIT(CopyB_i);
IA32_EMIT(Conv_FP2FP);
IA32_EMIT(Conv_I2I);
IA32_EMIT(Conv_I2I8Bit);
+ IA32_EMIT(Const);
+ IA32_EMIT(xCmp);
+ IA32_EMIT(xCmpSet);
+ IA32_EMIT(xCmpCMov);
+ IA32_EMIT2(fcomJmp, x87CondJmp);
+ IA32_EMIT2(fcompJmp, x87CondJmp);
+ IA32_EMIT2(fcomppJmp, x87CondJmp);
+ IA32_EMIT2(fcomrJmp, x87CondJmp);
+ IA32_EMIT2(fcomrpJmp, x87CondJmp);
+ IA32_EMIT2(fcomrppJmp, x87CondJmp);
/* benode emitter */
BE_EMIT(Call);
BE_EMIT(SetSP);
BE_EMIT(Copy);
BE_EMIT(Perm);
+ BE_EMIT(Return);
/* firm emitter */
EMIT(Jmp);
EMIT(Proj);
-#undef IA32_EMIT
#undef BE_EMIT
#undef EMIT
+#undef IA32_EMIT2
+#undef IA32_EMIT
}
/**
}
}
+/**
+ * Emits gas alignment directives
+ */
+static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
+ fprintf(F, "\t.p2align %u,,%u\n", align, skip);
+}
+
+/**
+ * Emits gas alignment directives for Functions depended on cpu architecture.
+ */
+static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
+ unsigned align; unsigned maximum_skip;
+
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ switch (cpu) {
+ case arch_i386:
+ align = 2; maximum_skip = 3;
+ break;
+ case arch_i486:
+ align = 4; maximum_skip = 15;
+ break;
+ case arch_k6:
+ align = 5; maximum_skip = 31;
+ break;
+ default:
+ align = 4; maximum_skip = 15;
+ }
+ ia32_emit_alignment(F, align, maximum_skip);
+}
+
+/**
+ * Emits gas alignment directives for Labels depended on cpu architecture.
+ */
+static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
+ unsigned align; unsigned maximum_skip;
+
+ /* gcc doesn't emit alignment for p4 ?*/
+ if (cpu == arch_pentium_4)
+ return;
+
+ switch (cpu) {
+ case arch_i386:
+ align = 2; maximum_skip = 3;
+ break;
+ case arch_i486:
+ align = 4; maximum_skip = 15;
+ break;
+ case arch_k6:
+ align = 5; maximum_skip = 7;
+ break;
+ default:
+ align = 4; maximum_skip = 7;
+ }
+ ia32_emit_alignment(F, align, maximum_skip);
+}
+
/**
* Walks over the nodes in a block connected by scheduling edges
* and emits code for each node.
*/
static void ia32_gen_block(ir_node *block, void *env) {
+ ia32_emit_env_t *emit_env = env;
const ir_node *irn;
+ int need_label = block != get_irg_start_block(get_irn_irg(block));
if (! is_Block(block))
return;
- fprintf(((ia32_emit_env_t *)env)->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+ if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
+ /* if the extended block scheduler is used, only leader blocks need
+ labels. */
+ need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
+ }
+
+ if (need_label) {
+ ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
+ fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+ }
+
sched_foreach(block, irn) {
ia32_emit_node(irn, env);
}
/**
* Emits code for function start.
*/
-static void ia32_emit_func_prolog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
entity *irg_ent = get_irg_entity(irg);
- const char *irg_name = get_entity_name(irg_ent);
+ const char *irg_name = get_entity_ld_name(irg_ent);
- fprintf(F, "\t.section\t.text\n");
+ fprintf(F, "\n");
+ ia32_switch_section(F, SECTION_TEXT);
+ ia32_emit_align_func(F, cpu);
if (get_entity_visibility(irg_ent) == visibility_external_visible) {
fprintf(F, ".globl %s\n", irg_name);
}
- fprintf(F, "\t.type\t%s, @function\n", irg_name);
+ ia32_dump_function_object(F, irg_name);
fprintf(F, "%s:\n", irg_name);
}
* Emits code for function end
*/
static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
- const char *irg_name = get_entity_name(get_irg_entity(irg));
+ const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
- fprintf(F, "\tret\n");
- fprintf(F, "\t.size\t%s, .-%s\n\n", irg_name, irg_name);
+ ia32_dump_function_size(F, irg_name);
+ fprintf(F, "\n");
}
/**
ia32_register_emitters();
- ia32_emit_func_prolog(F, irg);
+ ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
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