More missing config.h

[libfirm] / ir / be / ia32 / ia32_emitter.c

diff --git a/ir/be/ia32/ia32_emitter.c b/ir/be/ia32/ia32_emitter.c
index a992cf1..0afa23d 100644 (file)
--- a/ir/be/ia32/ia32_emitter.c
+++ b/ir/be/ia32/ia32_emitter.c
@@ -500,28 +500,6 @@ static const char *pointer_size(ir_mode *mode, int x87_insn)
        return NULL;
 }
 
-/**
- * Translate the stx names into %st(x).
- */
-static char *get_x87_reg_name(const arch_register_t *reg, char *buf) {
-       const char *name = arch_register_get_name(reg);
-
-       buf[0] = '%';
-       buf[1] = 's';
-       buf[2] = 't';
-
-       if (name[2] == '0')
-               buf[3] = '\0';
-       else {
-               buf[3] = '(';
-               buf[4] = name[2];
-               buf[5] = ')';
-               buf[6] = '\0';
-       }
-
-       return buf;
-}
-
 /**
  * Emits registers and/or address mode of a binary operation.
  */
@@ -551,7 +529,6 @@ const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
                                const arch_register_t *in2 = attr->x87[1];
                                const arch_register_t *out = attr->x87[2];
                                const arch_register_t *in;
-                               char                  buf1[7], buf2[7];
 
                                in  = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
                                out = out ? out : in1;
@@ -1174,8 +1151,7 @@ static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
                lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
        }
        else if (is_ia32_PsiCondSet(irn)) {
-               /* omit compare because flags are already set by And/Or */
-               snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+               lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, 0", irn);
        }
        else {
                assert(0 && "unsupported Set");
@@ -1810,9 +1786,10 @@ static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
        assert(cls1 == cls2 && "Register class mismatch at Perm");
 
        if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+#if 0
                if(emit_env->isa->opt_arch == arch_athlon) {
                        // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
-                       // it is nearly always beneficial to use the 3 xor trick instead of an xchg
+                       // it is often beneficial to use the 3 xor trick instead of an xchg
                        cmnt_buf[0] = 0;
                        lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
                        IA32_DO_EMIT(irn);
@@ -1820,8 +1797,11 @@ static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
                        IA32_DO_EMIT(irn);
                        lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
                } else {
+#endif
                        lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
+#if 0
                }
+#endif
        }
        else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
                lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,