return need_label;
}
-/**
- * Returns the register at in position pos.
- */
-static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
-{
- ir_node *op;
- const arch_register_t *reg = NULL;
-
- assert(get_irn_arity(irn) > pos && "Invalid IN position");
-
- /* The out register of the operator at position pos is the
- in register we need. */
- op = get_irn_n(irn, pos);
-
- reg = arch_get_irn_register(op);
-
- assert(reg && "no in register found");
-
- if (reg == &ia32_registers[REG_GP_NOREG])
- panic("trying to emit noreg for %+F input %d", irn, pos);
-
- return reg;
-}
-
-/**
- * Returns the register at out position pos.
- */
-static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
-{
- ir_node *proj;
- const arch_register_t *reg = NULL;
-
- /* 1st case: irn is not of mode_T, so it has only */
- /* one OUT register -> good */
- /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
- /* Proj with the corresponding projnum for the register */
-
- if (get_irn_mode(irn) != mode_T) {
- assert(pos == 0);
- reg = arch_get_irn_register(irn);
- } else if (is_ia32_irn(irn)) {
- reg = arch_irn_get_register(irn, pos);
- } else {
- const ir_edge_t *edge;
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "non-Proj from mode_T node");
- if (get_Proj_proj(proj) == pos) {
- reg = arch_get_irn_register(proj);
- break;
- }
- }
- }
-
- assert(reg && "no out register found");
- return reg;
-}
-
/**
* Add a number to a prefix. This number will not be used a second time.
*/
void ia32_emit_source_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_in_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_in(node, pos);
emit_register(reg, NULL);
}
return;
}
- reg = get_in_reg(node, pos);
+ reg = arch_get_irn_register_in(node, pos);
emit_8bit_register(reg);
}
void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_in_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_in(node, pos);
emit_8bit_register_high(reg);
}
return;
}
- reg = get_in_reg(node, pos);
+ reg = arch_get_irn_register_in(node, pos);
emit_16bit_register(reg);
}
void ia32_emit_dest_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_out_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pos);
emit_register(reg, NULL);
}
void ia32_emit_dest_register_size(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_out_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pos);
emit_register(reg, get_ia32_ls_mode(node));
}
void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
{
- const arch_register_t *reg = get_out_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pos);
emit_register(reg, mode_Bu);
}
emit_ia32_Immediate(in);
} else {
const ir_mode *mode = get_ia32_ls_mode(node);
- const arch_register_t *reg = get_in_reg(node, pos);
+ const arch_register_t *reg = arch_get_irn_register_in(node, pos);
emit_register(reg, mode);
}
}
int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
/* just to be sure... */
assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
/* emit base */
if (has_base) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_base);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
emit_register(reg, NULL);
}
/* emit index + scale */
if (has_index) {
- const arch_register_t *reg = get_in_reg(node, n_ia32_index);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
int scale;
be_emit_char(',');
emit_register(reg, NULL);
end_of_mods:
switch (*fmt++) {
+ arch_register_t const *reg;
+ ir_node const *imm;
+
case '%':
be_emit_char('%');
break;
ia32_emit_am(node);
break;
- case 'R': {
- const arch_register_t *reg = va_arg(ap, const arch_register_t*);
+ case 'R':
+ reg = va_arg(ap, const arch_register_t*);
if (get_ia32_op_type(node) == ia32_AddrModeS) {
goto emit_AM;
} else {
- if (mod & EMIT_ALTERNATE_AM)
- be_emit_char('*');
- emit_register(reg, NULL);
+ goto emit_R;
}
- break;
- }
case 'S':
if (get_ia32_op_type(node) == ia32_AddrModeS) {
assert(get_ia32_op_type(node) == ia32_Normal);
goto emit_S;
}
- break;
default: goto unknown;
}
break;
}
- case 'D': {
- unsigned pos;
- const arch_register_t *reg;
-
+ case 'D':
if (*fmt < '0' || '9' <= *fmt)
goto unknown;
-
- pos = *fmt++ - '0';
- reg = get_out_reg(node, pos);
- emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
- break;
- }
+ reg = arch_get_irn_register_out(node, *fmt++ - '0');
+ goto emit_R;
case 'I':
+ imm = node;
+emit_I:
if (!(mod & EMIT_ALTERNATE_AM))
be_emit_char('$');
- emit_ia32_Immediate_no_prefix(node);
+ emit_ia32_Immediate_no_prefix(imm);
break;
case 'L':
ia32_emit_cfop_target(node);
break;
- case 'M': {
+ case 'M':
ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
break;
- }
case 'P': {
ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
break;
}
- case 'R': {
- const arch_register_t *reg = va_arg(ap, const arch_register_t*);
+ case 'R':
+ reg = va_arg(ap, const arch_register_t*);
+emit_R:
+ if (mod & EMIT_ALTERNATE_AM)
+ be_emit_char('*');
if (mod & EMIT_HIGH_REG) {
emit_8bit_register_high(reg);
} else if (mod & EMIT_LOW_REG) {
emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
}
break;
- }
emit_S:
case 'S': {
- unsigned pos;
- const ir_node *in;
+ unsigned pos;
if (*fmt < '0' || '9' <= *fmt)
goto unknown;
pos = *fmt++ - '0';
- in = get_irn_n(node, pos);
- if (is_ia32_Immediate(in)) {
- if (!(mod & EMIT_ALTERNATE_AM))
- be_emit_char('$');
- emit_ia32_Immediate_no_prefix(in);
+ imm = get_irn_n(node, pos);
+ if (is_ia32_Immediate(imm)) {
+ goto emit_I;
} else {
- const arch_register_t *reg;
-
- if (mod & EMIT_ALTERNATE_AM)
- be_emit_char('*');
- reg = get_in_reg(node, pos);
- emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
+ reg = arch_get_irn_register_in(node, pos);
+ goto emit_R;
}
- break;
}
case 's': {
static void emit_ia32_IMul(const ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_IMul_left);
- const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
+ const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
/* do we need the 3-address form? */
if (is_ia32_NoReg_GP(left) ||
- get_in_reg(node, n_ia32_IMul_left) != out_reg) {
+ arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
} else {
ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
} else if (is_ia32_Load(pred)) {
return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
+ } else if (is_ia32_Store(pred)) {
+ return find_original_value(get_irn_n(pred, n_ia32_Store_val));
} else {
return node;
}
- } else if (is_ia32_Store(node)) {
- return find_original_value(get_irn_n(node, n_ia32_Store_val));
} else if (is_Phi(node)) {
int i, arity;
arity = get_irn_arity(node);
*/
static void emit_ia32_Setcc(const ir_node *node)
{
- const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
+ const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
ia32_condition_code_t cc = get_ia32_condcode(node);
cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
static void emit_ia32_CMovcc(const ir_node *node)
{
const ia32_attr_t *attr = get_ia32_attr_const(node);
- const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
ia32_condition_code_t cc = get_ia32_condcode(node);
const arch_register_t *in_true;
const arch_register_t *in_false;
ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
}
-
-/* jump table entry (target and corresponding number) */
-typedef struct branch_t {
- ir_node *target;
- int value;
-} branch_t;
-
-/* jump table for switch generation */
-typedef struct jmp_tbl_t {
- ir_node *defProj; /**< default target */
- long min_value; /**< smallest switch case */
- long max_value; /**< largest switch case */
- long num_branches; /**< number of jumps */
- char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
- branch_t *branches; /**< jump array */
-} jmp_tbl_t;
-
/**
- * Compare two variables of type branch_t. Used to sort all switch cases
- */
-static int ia32_cmp_branch_t(const void *a, const void *b)
-{
- branch_t *b1 = (branch_t *)a;
- branch_t *b2 = (branch_t *)b;
-
- if (b1->value <= b2->value)
- return -1;
- else
- return 1;
-}
-
-static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
-{
- int i;
- long default_pn = get_ia32_default_pn(node);
- ir_node *proj;
- const ir_edge_t *edge;
-
- /* fill the table structure */
- get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
- tbl->defProj = NULL;
- tbl->num_branches = get_irn_n_edges(node) - 1;
- tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
- tbl->min_value = LONG_MAX;
- tbl->max_value = LONG_MIN;
-
- i = 0;
- /* go over all proj's and collect them */
- foreach_out_edge(node, edge) {
- long pn;
- proj = get_edge_src_irn(edge);
- assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
-
- pn = get_Proj_proj(proj);
-
- /* check for default proj */
- if (pn == default_pn) {
- assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
- tbl->defProj = proj;
- } else {
- tbl->min_value = pn < tbl->min_value ? pn : tbl->min_value;
- tbl->max_value = pn > tbl->max_value ? pn : tbl->max_value;
-
- /* create branch entry */
- tbl->branches[i].target = proj;
- tbl->branches[i].value = pn;
- ++i;
- }
-
- }
- assert(i == tbl->num_branches);
-
- /* sort the branches by their number */
- qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
-}
-
-/**
- * Emits code for a SwitchJmp (creates a jump table if
- * possible otherwise a cmp-jmp cascade). Port from
- * cggg ia32 backend
+ * Emits code for a SwitchJmp
*/
static void emit_ia32_SwitchJmp(const ir_node *node)
{
- unsigned long interval;
- int last_value, i;
- jmp_tbl_t tbl;
-
- /* fill the table structure */
- generate_jump_table(&tbl, node);
-
- /* two-complement's magic make this work without overflow */
- interval = tbl.max_value - tbl.min_value;
+ ir_entity *jump_table = get_ia32_am_sc(node);
+ long default_pn = get_ia32_default_pn(node);
- /* emit the table */
- ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
- ia32_emitf(tbl.defProj, "\tja %L\n");
-
- if (tbl.num_branches > 1) {
- /* create table */
- ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
-
- be_gas_emit_switch_section(GAS_SECTION_RODATA);
- ia32_emitf(NULL, "\t.align 4\n");
- ia32_emitf(NULL, "%s:\n", tbl.label);
-
- last_value = tbl.branches[0].value;
- for (i = 0; i != tbl.num_branches; ++i) {
- while (last_value != tbl.branches[i].value) {
- ia32_emitf(tbl.defProj, ".long %L\n");
- ++last_value;
- }
- ia32_emitf(tbl.branches[i].target, ".long %L\n");
- ++last_value;
- }
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- } else {
- /* one jump is enough */
- ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
- }
-
- free(tbl.branches);
+ ia32_emitf(node, "\tjmp %*AM\n");
+ emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
}
/**
*/
static void emit_ia32_Jmp(const ir_node *node)
{
- ir_node *block;
-
- /* for now, the code works for scheduled and non-schedules blocks */
- block = get_nodes_block(node);
-
/* we have a block schedule */
if (can_be_fallthrough(node)) {
ia32_emitf(node, "\t/* fallthrough to %L */\n");
/* get register */
if (asm_reg->use_input == 0) {
- reg = get_out_reg(node, asm_reg->inout_pos);
+ reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
} else {
ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
emit_ia32_Immediate(pred);
return s;
}
- reg = get_in_reg(node, asm_reg->inout_pos);
+ reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
}
if (reg == NULL) {
ir_fprintf(stderr,
*/
static void emit_ia32_Conv_I2I(const ir_node *node)
{
- ir_mode *smaller_mode = get_ia32_ls_mode(node);
- int signed_mode = mode_is_signed(smaller_mode);
+ ir_mode *smaller_mode = get_ia32_ls_mode(node);
+ int signed_mode = mode_is_signed(smaller_mode);
const char *sign_suffix;
assert(!mode_is_float(smaller_mode));
static void emit_ia32_Minus64Bit(const ir_node *node)
{
- const arch_register_t *in_lo = get_in_reg(node, 0);
- const arch_register_t *in_hi = get_in_reg(node, 1);
- const arch_register_t *out_lo = get_out_reg(node, 0);
- const arch_register_t *out_hi = get_out_reg(node, 1);
+ const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
+ const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
+ const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
+ const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
if (out_lo == in_lo) {
if (out_hi != in_hi) {
*/
static void ia32_emit_block_header(ir_node *block)
{
- ir_graph *irg = current_ir_graph;
+ ir_graph *irg = current_ir_graph;
int need_label = block_needs_label(block);
- int i, arity;
- ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
+ ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
+ int arity;
if (block == get_irg_end_block(irg))
return;
if (arity <= 0) {
be_emit_cstring(" none");
} else {
+ int i;
for (i = 0; i < arity; ++i) {
ir_node *predblock = get_Block_cfgpred_block(block, i);
be_emit_irprintf(" %d", get_irn_node_nr(predblock));
Those are ascending with ascending addresses. */
qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
{
- size_t i;
+ size_t e;
- for (i = 0; i < ARR_LEN(exc_list); ++i) {
+ for (e = 0; e < ARR_LEN(exc_list); ++e) {
be_emit_cstring("\t.long ");
- ia32_emit_exc_label(exc_list[i].exc_instr);
+ ia32_emit_exc_label(exc_list[e].exc_instr);
be_emit_char('\n');
be_emit_cstring("\t.long ");
- be_gas_emit_block_name(exc_list[i].block);
+ be_gas_emit_block_name(exc_list[e].block);
be_emit_char('\n');
}
}
int offs = get_ia32_am_offs_int(node);
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
unsigned modrm = 0;
unsigned sib = 0;
unsigned emitoffs = 0;
/* Determine if we need a SIB byte. */
if (has_index) {
- const arch_register_t *reg_index = arch_get_irn_register(index);
+ const arch_register_t *reg_index = arch_get_irn_register(idx);
int scale = get_ia32_am_scale(node);
assert(scale < 4);
/* R/M set to ESP means SIB in 32bit mode. */
if (get_ia32_op_type(node) == ia32_AddrModeS) {
bemit_mod_am(ruval, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
bemit_modru(reg, ruval);
}
bemit8((unsigned char)attr->offset);
bemit8(opcode);
bemit_mod_am(ruval, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
if (reg->index == REG_GP_EAX) {
bemit8(opcode_ax);
} else {
*/
static void bemit_binop_2(const ir_node *node, unsigned code)
{
- const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
bemit8(code);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
+ const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
bemit_modrr(op2, out);
} else {
bemit_mod_am(reg_gp_map[out->index], node);
{
bemit8(code);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, input);
+ const arch_register_t *in = arch_get_irn_register_in(node, input);
bemit_modru(in, ext);
} else {
bemit_mod_am(ext, node);
static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit_unop(node, code, reg_gp_map[out->index], input);
}
static void bemit_copy(const ir_node *copy)
{
- const arch_register_t *in = get_in_reg(copy, 0);
- const arch_register_t *out = get_out_reg(copy, 0);
+ const arch_register_t *in = arch_get_irn_register_in(copy, 0);
+ const arch_register_t *out = arch_get_irn_register_out(copy, 0);
if (in == out)
return;
static void bemit_xor0(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x31);
bemit_modrr(out, out);
}
static void bemit_mov_const(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0xB8 + reg_gp_map[out->index]);
bemit_immediate(node, false);
}
} \
} else { \
bemit8(ext << 3 | 1); \
- bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
+ bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
} \
} \
\
bemit8(get_ia32_immediate_attr_const(val)->offset); \
} else { \
bemit8(ext << 3); \
- bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
+ bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
} \
}
#define SHIFT(op, ext) \
static void bemit_##op(const ir_node *node) \
{ \
- const arch_register_t *out = get_out_reg(node, 0); \
+ const arch_register_t *out = arch_get_irn_register_out(node, 0); \
ir_node *count = get_irn_n(node, 1); \
if (is_ia32_Immediate(count)) { \
int offset = get_ia32_immediate_attr_const(count)->offset; \
static void bemit_shld(const ir_node *node)
{
- const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
- const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
bemit8(0x0F);
if (is_ia32_Immediate(count)) {
static void bemit_shrd(const ir_node *node)
{
- const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
- const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
bemit8(0x0F);
if (is_ia32_Immediate(count)) {
*/
static void bemit_setcc(const ir_node *node)
{
- const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
+ const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
ia32_condition_code_t cc = get_ia32_condcode(node);
cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
{
const ia32_attr_t *attr = get_ia32_attr_const(node);
int ins_permuted = attr->data.ins_permuted;
- const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
ia32_condition_code_t cc = get_ia32_condcode(node);
const arch_register_t *in_true;
const arch_register_t *in_false;
if (get_ia32_op_type(node) == ia32_AddrModeS) {
bemit_mod_am(7, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
bemit_modru(reg, 7);
}
bemit8((unsigned char)attr->offset);
bemit8(0x81);
bemit_mod_am(7, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
if (reg->index == REG_GP_EAX) {
bemit8(0x3D);
} else {
}
panic("invalid imm size?!?");
} else {
- const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
bemit8(0x3B);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
+ const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
bemit_modrr(op2, out);
} else {
bemit_mod_am(reg_gp_map[out->index], node);
ir_node *right = get_irn_n(node, n_ia32_binary_right);
if (is_ia32_Immediate(right)) {
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
if (out->index == REG_GP_EAX) {
bemit8(0x3C);
} else {
}
bemit8(get_ia32_immediate_attr_const(right)->offset);
} else {
- const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
bemit8(0x3A);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
bemit_modrr(out, in);
} else {
bemit_mod_am(reg_gp_map[out->index], node);
ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
if (is_ia32_Immediate(right)) {
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
if (out->index == REG_GP_EAX) {
bemit8(0xA8);
} else {
}
bemit8(get_ia32_immediate_attr_const(right)->offset);
} else {
- const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
+ const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
bemit8(0x84);
if (get_ia32_op_type(node) == ia32_Normal) {
- const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
bemit_modrr(out, in);
} else {
bemit_mod_am(reg_gp_map[out->index], node);
static void bemit_dec(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
bemit8(0x48 + reg_gp_map[out->index]);
}
static void bemit_inc(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
+ const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
bemit8(0x40 + reg_gp_map[out->index]);
}
static void bemit_ldtls(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x65); // gs:
if (out->index == REG_GP_EAX) {
*/
static void bemit_lea(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
bemit8(0x8D);
bemit_mod_am(reg_gp_map[out->index], node);
}
static void bemit_minus64bit(const ir_node *node)
{
- const arch_register_t *in_lo = get_in_reg(node, 0);
- const arch_register_t *in_hi = get_in_reg(node, 1);
- const arch_register_t *out_lo = get_out_reg(node, 0);
- const arch_register_t *out_hi = get_out_reg(node, 1);
+ const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
+ const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
+ const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
+ const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
if (out_lo == in_lo) {
if (out_hi != in_hi) {
*/
static void bemit_load(const ir_node *node)
{
- const arch_register_t *out = get_out_reg(node, 0);
+ const arch_register_t *out = arch_get_irn_register_out(node, 0);
if (out->index == REG_GP_EAX) {
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
if (!has_base && !has_index) {
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
bemit_immediate(value, false);
}
} else {
- const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
+ const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
if (in->index == REG_GP_EAX) {
ir_node *base = get_irn_n(node, n_ia32_base);
int has_base = !is_ia32_NoReg_GP(base);
- ir_node *index = get_irn_n(node, n_ia32_index);
- int has_index = !is_ia32_NoReg_GP(index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
+ int has_index = !is_ia32_NoReg_GP(idx);
if (!has_base && !has_index) {
ir_entity *ent = get_ia32_am_sc(node);
int offs = get_ia32_am_offs_int(node);
bemit8(0xFF);
bemit_mod_am(6, node);
} else {
- const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
+ const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
bemit8(0x50 + reg_gp_map[reg->index]);
}
}
*/
static void bemit_pop(const ir_node *node)
{
- const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
+ const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
bemit8(0x58 + reg_gp_map[reg->index]);
}
const ir_node *proj_false;
const ir_node *dest_true;
const ir_node *dest_false;
- const ir_node *block;
cc = determine_final_cc(node, 0, cc);
proj_false = get_proj(node, pn_ia32_Jcc_false);
assert(proj_false && "Jcc without false Proj");
- block = get_nodes_block(node);
-
if (can_be_fallthrough(proj_true)) {
/* exchange both proj's so the second one can be omitted */
const ir_node *t = proj_true;
static void bemit_switchjmp(const ir_node *node)
{
- unsigned long interval;
- int last_value;
- int i;
- jmp_tbl_t tbl;
- const arch_register_t *in;
+ ir_entity *jump_table = get_ia32_am_sc(node);
+ long default_pn = get_ia32_default_pn(node);
- /* fill the table structure */
- generate_jump_table(&tbl, node);
-
- /* two-complement's magic make this work without overflow */
- interval = tbl.max_value - tbl.min_value;
-
- in = get_in_reg(node, 0);
- /* emit the table */
- if (get_signed_imm_size(interval) == 1) {
- bemit8(0x83); // cmpl $imm8, %in
- bemit_modru(in, 7);
- bemit8(interval);
- } else {
- bemit8(0x81); // cmpl $imm32, %in
- bemit_modru(in, 7);
- bemit32(interval);
- }
- bemit8(0x0F); // ja tbl.defProj
- bemit8(0x87);
- ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
-
- if (tbl.num_branches > 1) {
- /* create table */
- bemit8(0xFF); // jmp *tbl.label(,%in,4)
- bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
- bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
- be_emit_irprintf("\t.long %s\n", tbl.label);
-
- be_gas_emit_switch_section(GAS_SECTION_RODATA);
- be_emit_cstring(".align 4\n");
- be_emit_irprintf("%s:\n", tbl.label);
-
- last_value = tbl.branches[0].value;
- for (i = 0; i != tbl.num_branches; ++i) {
- while (last_value != tbl.branches[i].value) {
- ia32_emitf(tbl.defProj, ".long %L\n");
- ++last_value;
- }
- ia32_emitf(tbl.branches[i].target, ".long %L\n");
- ++last_value;
- }
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- } else {
- /* one jump is enough */
- panic("switch only has one case");
- //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
- }
-
- be_emit_write_line();
+ bemit8(0xFF); // jmp *tbl.label(,%in,4)
+ bemit_mod_am(0x05, node);
- free(tbl.branches);
+ emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
}
/**
bemit_sub(node);
/* mov %esp, %out */
bemit8(0x8B);
- out = get_out_reg(node, 1);
+ out = arch_get_irn_register_out(node, 1);
bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
}
size = get_signed_imm_size(offs);
bemit8(size == 1 ? 0x83 : 0x81);
- reg = get_out_reg(node, 0);
+ reg = arch_get_irn_register_out(node, 0);
bemit_modru(reg, ext);
if (size == 1) {
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