ir_type *res;
if (! e) {
- char buf[64];
- snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
- res = new_type_primitive(new_id_from_str(buf), mode);
+ res = new_type_primitive(mode);
if (get_mode_size_bits(mode) >= 80) {
set_type_alignment_bytes(res, 16);
}
res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
set_entity_ld_ident(res, get_entity_ident(res));
- set_entity_visibility(res, visibility_local);
- set_entity_variability(res, variability_constant);
- set_entity_allocation(res, allocation_static);
+ set_entity_linkage(res, IR_LINKAGE_LOCAL | IR_LINKAGE_CONSTANT);
/* we create a new entity here: It's initialization must resist on the
const code irg */
int clobbers_flags = 0;
unsigned clobber_bits[N_CLASSES];
int out_size;
+ backend_info_t *info;
memset(&clobber_bits, 0, sizeof(clobber_bits));
++out_idx;
}
- /* Attempt to make ASM node register pressure faithfull.
+ /* Attempt to make ASM node register pressure faithful.
* (This does not work for complicated cases yet!)
*
* Algorithm: Check if there are fewer inputs or outputs (I will call this
if (arity == 0)
be_dep_on_frame(new_node);
- set_ia32_out_req_all(new_node, out_reg_reqs);
+ info = be_get_info(new_node);
+ for (i = 0; i < out_arity; ++i) {
+ info->out_infos[i].req = out_reg_reqs[i];
+ }
set_ia32_in_req_all(new_node, in_reg_reqs);
SET_IA32_ORIG_NODE(new_node, node);