#include "irprintf.h"
#include "typerep.h"
#include "bitset.h"
+#include "heights.h"
#include "../betranshlp.h"
#include "../beirg.h"
#include "gen_ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
-/** hold the current code generator during transformation */
-ia32_code_gen_t *env_cg = NULL;
-
-heights_t *heights = NULL;
-
-static const arch_register_req_t no_register_req = {
- arch_register_req_type_none,
- NULL, /* regclass */
- NULL, /* limit bitset */
- 0, /* same pos */
- 0 /* different pos */
-};
+ir_heights_t *ia32_heights = NULL;
static int check_immediate_constraint(long val, char immediate_constraint_type)
{
*/
static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
{
- ir_type *res = pmap_get(types, mode);
+ ir_type *res = (ir_type*)pmap_get(types, mode);
if (res != NULL)
return res;
return res;
}
-ir_entity *create_float_const_entity(ir_node *cnst)
+ir_entity *ia32_create_float_const_entity(ir_node *cnst)
{
- ia32_isa_t *isa = env_cg->isa;
- tarval *tv = get_Const_tarval(cnst);
- ir_entity *res = pmap_get(isa->tv_ent, tv);
+ ir_graph *irg = get_irn_irg(cnst);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_isa_t *isa = (ia32_isa_t*) arch_env;
+ ir_tarval *tv = get_Const_tarval(cnst);
+ ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv);
ir_initializer_t *initializer;
ir_mode *mode;
ir_type *tp;
ir_graph *irg = current_ir_graph;
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst,
- symconst_sign, no_pic_adjust, val);
- arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
+ symconst_sign, ia32_no_pic_adjust, val);
+ arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
return immediate;
}
/* TODO: construct a hashmap instead of doing linear search for clobber
* register */
- for (c = 0; c < N_CLASSES; ++c) {
+ for (c = 0; c < N_IA32_CLASSES; ++c) {
cls = & ia32_reg_classes[c];
for (r = 0; r < cls->n_regs; ++r) {
const arch_register_t *temp_reg = arch_register_for_index(cls, r);
int ia32_mode_needs_gp_reg(ir_mode *mode)
{
- if (mode == mode_fpcw)
+ if (mode == ia32_mode_fpcw)
return 0;
if (get_mode_size_bits(mode) > 32)
return 0;
case 'a':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX;
+ limited |= 1 << REG_GP_EAX;
break;
case 'b':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EBX;
+ limited |= 1 << REG_GP_EBX;
break;
case 'c':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ECX;
+ limited |= 1 << REG_GP_ECX;
break;
case 'd':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDX;
+ limited |= 1 << REG_GP_EDX;
break;
case 'D':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDI;
+ limited |= 1 << REG_GP_EDI;
break;
case 'S':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ESI;
+ limited |= 1 << REG_GP_ESI;
break;
case 'Q':
case 'q':
* difference to Q for us (we only assign whole registers) */
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX;
+ limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
+ 1 << REG_GP_EDX;
break;
case 'A':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EDX;
+ limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX;
break;
case 'l':
assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
- 1 << REG_EBP;
+ limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX |
+ 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI |
+ 1 << REG_GP_EBP;
break;
case 'R':
#endif
}
-ir_node *gen_ASM(ir_node *node)
+ir_node *ia32_gen_ASM(ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_node *new_block = get_new_node(block);
const ir_asm_constraint *out_constraints;
ident **clobbers;
int clobbers_flags = 0;
- unsigned clobber_bits[N_CLASSES];
+ unsigned clobber_bits[N_IA32_CLASSES];
int out_size;
backend_info_t *info;
continue;
}
- req = parse_clobber(c);
+ req = ia32_parse_clobber(c);
clobber_bits[req->cls->index] |= *req->limited;
n_clobbers++;
/* construct output constraints */
out_size = out_arity + 1;
- out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0]));
+ out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size);
for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
const ir_asm_constraint *constraint = &out_constraints[out_idx];
const arch_register_req_t *req;
parse_asm_constraints(&parsed_constraint, c, 1);
- req = make_register_req(&parsed_constraint, n_out_constraints,
+ req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
out_reg_reqs, out_idx);
out_reg_reqs[out_idx] = req;
}
/* inputs + input constraints */
- in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
+ in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity);
for (i = 0; i < arity; ++i) {
ir_node *pred = get_irn_n(node, i);
const ir_asm_constraint *constraint = &in_constraints[i];
if (r_clobber_bits != 0) {
if (parsed_constraint.all_registers_allowed) {
parsed_constraint.all_registers_allowed = 0;
- be_abi_set_non_ignore_regs(be_get_irg_abi(env_cg->irg),
+ be_set_allocatable_regs(current_ir_graph,
parsed_constraint.cls,
&parsed_constraint.allowed_registers);
}
}
}
- req = make_register_req(&parsed_constraint, n_out_constraints,
+ req = ia32_make_register_req(&parsed_constraint, n_out_constraints,
out_reg_reqs, i);
in_reg_reqs[i] = req;
if (parsed_constraint.immediate_type != '\0') {
char imm_type = parsed_constraint.immediate_type;
- input = try_create_Immediate(pred, imm_type);
+ input = ia32_try_create_Immediate(pred, imm_type);
}
if (input == NULL) {
if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
continue;
- req = parse_clobber(c);
+ req = ia32_parse_clobber(c);
out_reg_reqs[out_idx] = req;
++out_idx;
}
ir_node **new_in;
in_size *= 2;
- new_in_reg_reqs
- = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0]));
+ new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*,
+ in_size);
memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0]));
new_in = ALLOCANZ(ir_node*, in_size);
memcpy(new_in, in, arity*sizeof(new_in[0]));
assert(outreq->type & arch_register_req_type_limited);
in_reg_reqs[arity] = outreq;
in[arity] = new_bd_ia32_ProduceVal(NULL, block);
- be_dep_on_frame(in[arity]);
++arity;
}
} else {
out_size *= 2;
new_out_reg_reqs
- = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
+ = OALLOCN(obst, const arch_register_req_t*, out_size);
memcpy(new_out_reg_reqs, out_reg_reqs,
out_arity * sizeof(new_out_reg_reqs[0]));
out_reg_reqs = new_out_reg_reqs;
out_size = out_arity + 1;
new_out_reg_reqs
- = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0]));
+ = OALLOCN(obst, const arch_register_req_t*, out_size);
memcpy(new_out_reg_reqs, out_reg_reqs,
out_arity * sizeof(new_out_reg_reqs[0]));
out_reg_reqs = new_out_reg_reqs;
new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity,
get_ASM_text(node), register_map);
- if (arity == 0)
- be_dep_on_frame(new_node);
-
info = be_get_info(new_node);
for (i = 0; i < out_arity; ++i) {
info->out_infos[i].req = out_reg_reqs[i];
}
- set_ia32_in_req_all(new_node, in_reg_reqs);
+ arch_set_in_register_reqs(new_node, in_reg_reqs);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
-ir_node *gen_CopyB(ir_node *node)
+ir_node *ia32_gen_CopyB(ir_node *node)
{
ir_node *block = get_new_node(get_nodes_block(node));
ir_node *src = get_CopyB_src(node);
size >>= 2;
res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size);
- be_dep_on_frame(res);
res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem);
} else {
return res;
}
-ir_node *gen_Proj_tls(ir_node *node)
+ir_node *ia32_gen_Proj_tls(ir_node *node)
{
ir_node *block = get_new_node(get_nodes_block(node));
- ir_node *res = NULL;
-
- res = new_bd_ia32_LdTls(NULL, block, mode_Iu);
-
+ ir_node *res = new_bd_ia32_LdTls(NULL, block);
return res;
}
-ir_node *gen_Unknown(ir_node *node)
+ir_node *ia32_gen_Unknown(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
ir_graph *irg = current_ir_graph;
panic("unsupported Unknown-Mode");
}
- be_dep_on_frame(res);
return res;
}
-const arch_register_req_t *make_register_req(const constraint_t *constraint,
+const arch_register_req_t *ia32_make_register_req(const constraint_t *constraint,
int n_outs, const arch_register_req_t **out_reqs, int pos)
{
struct obstack *obst = get_irg_obstack(current_ir_graph);
other_constr = out_reqs[same_as];
- req = obstack_alloc(obst, sizeof(req[0]));
+ req = OALLOC(obst, arch_register_req_t);
*req = *other_constr;
req->type |= arch_register_req_type_should_be_same;
req->other_same = 1U << pos;
+ req->width = 1;
/* switch constraints. This is because in firm we have same_as
* constraints on the output constraints while in the gcc asm syntax
/* pure memory ops */
if (constraint->cls == NULL) {
- return &no_register_req;
+ return arch_no_register_req;
}
if (constraint->allowed_registers != 0
&& !constraint->all_registers_allowed) {
unsigned *limited_ptr;
- req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
+ req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
memset(req, 0, sizeof(req[0]));
limited_ptr = (unsigned*) (req+1);
*limited_ptr = constraint->allowed_registers;
req->limited = limited_ptr;
} else {
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
+ req = OALLOCZ(obst, arch_register_req_t);
req->type = arch_register_req_type_normal;
}
- req->cls = constraint->cls;
+ req->cls = constraint->cls;
+ req->width = 1;
return req;
}
-const arch_register_req_t *parse_clobber(const char *clobber)
+const arch_register_req_t *ia32_parse_clobber(const char *clobber)
{
struct obstack *obst = get_irg_obstack(current_ir_graph);
const arch_register_t *reg = ia32_get_clobber_register(clobber);
assert(reg->index < 32);
- limited = obstack_alloc(obst, sizeof(limited[0]));
+ limited = OALLOC(obst, unsigned);
*limited = 1 << reg->index;
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
+ req = OALLOCZ(obst, arch_register_req_t);
req->type = arch_register_req_type_limited;
req->cls = arch_register_get_class(reg);
req->limited = limited;
+ req->width = 1;
return req;
}
-int prevents_AM(ir_node *const block, ir_node *const am_candidate,
+int ia32_prevents_AM(ir_node *const block, ir_node *const am_candidate,
ir_node *const other)
{
if (get_nodes_block(other) != block)
if (is_Proj(pred) && get_Proj_pred(pred) == am_candidate)
continue;
- if (!heights_reachable_in_block(heights, pred, am_candidate))
+ if (!heights_reachable_in_block(ia32_heights, pred, am_candidate))
continue;
return 1;
if (is_Proj(other) && get_Proj_pred(other) == am_candidate)
return 0;
- if (!heights_reachable_in_block(heights, other, am_candidate))
+ if (!heights_reachable_in_block(ia32_heights, other, am_candidate))
return 0;
return 1;
}
}
-ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
+ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type)
{
- long val = 0;
- ir_entity *symconst_ent = NULL;
- ir_mode *mode;
- ir_node *cnst = NULL;
- ir_node *symconst = NULL;
- ir_node *new_node;
+ long val = 0;
+ ir_entity *symconst_ent = NULL;
+ ir_mode *mode;
+ ir_node *cnst = NULL;
+ ir_node *symconst = NULL;
+ ir_node *new_node;
mode = get_irn_mode(node);
if (!mode_is_int(mode) && !mode_is_reference(mode)) {
if (is_Const(node)) {
cnst = node;
symconst = NULL;
- } else if (is_Global(node)) {
+ } else if (is_SymConst_addr_ent(node)
+ && get_entity_owner(get_SymConst_entity(node)) != get_tls_type()) {
cnst = NULL;
symconst = node;
} else if (is_Add(node)) {
ir_node *left = get_Add_left(node);
ir_node *right = get_Add_right(node);
- if (is_Const(left) && is_Global(right)) {
+ if (is_Const(left) && is_SymConst_addr_ent(right)) {
cnst = left;
symconst = right;
- } else if (is_Global(left) && is_Const(right)) {
+ } else if (is_SymConst_addr_ent(left) && is_Const(right)) {
cnst = right;
symconst = left;
}
}
if (cnst != NULL) {
- tarval *offset = get_Const_tarval(cnst);
+ ir_tarval *offset = get_Const_tarval(cnst);
if (!tarval_is_long(offset)) {
ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst);
return NULL;
projects / libfirm / blobdiff