sparc: remove unnecessary convs before stores

[libfirm] / ir / be / ia32 / ia32_architecture.c

diff --git a/ir/be/ia32/ia32_architecture.c b/ir/be/ia32/ia32_architecture.c
index 78bca5a..0e93077 100644 (file)
--- a/ir/be/ia32/ia32_architecture.c
+++ b/ir/be/ia32/ia32_architecture.c
@@ -150,7 +150,7 @@ static int         opt_size             = 0;
 static int         emit_machcode        = 0;
 static cpu_support arch                 = cpu_generic;
 static cpu_support opt_arch             = cpu_generic;
-static int         use_sse2             = 0;
+static int         fpu_arch             = 0;
 static int         opt_cc               = 1;
 static int         opt_unsafe_floatconv = 0;
 
@@ -222,29 +222,24 @@ static lc_opt_enum_int_var_t opt_arch_var = {
 };
 
 static const lc_opt_enum_int_items_t fp_unit_items[] = {
-       { "x87" ,    0 },
-       { "sse2",    1 },
-       { NULL,      0 }
+       { "x87" ,      IA32_FPU_ARCH_X87 },
+       { "sse2",      IA32_FPU_ARCH_SSE2 },
+       { "softfloat", IA32_FPU_ARCH_SOFTFLOAT },
+       { NULL,        IA32_FPU_ARCH_NONE }
 };
 
 static lc_opt_enum_int_var_t fp_unit_var = {
-       &use_sse2, fp_unit_items
+       &fpu_arch, fp_unit_items
 };
 
 static const lc_opt_table_entry_t ia32_architecture_options[] = {
-       LC_OPT_ENT_BOOL("size",            "optimize for size", &opt_size),
-       LC_OPT_ENT_ENUM_INT("arch",        "select the instruction architecture",
-                           &arch_var),
-       LC_OPT_ENT_ENUM_INT("opt",         "optimize for instruction architecture",
-                           &opt_arch_var),
-       LC_OPT_ENT_ENUM_INT("fpunit",      "select the floating point unit",
-                           &fp_unit_var),
-       LC_OPT_ENT_NEGBIT("nooptcc",       "do not optimize calling convention",
-                         &opt_cc, 1),
-       LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
-                      "optimisations", &opt_unsafe_floatconv, 1),
-       LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
-                       &emit_machcode),
+       LC_OPT_ENT_BOOL    ("size",             "optimize for size",                                  &opt_size),
+       LC_OPT_ENT_ENUM_INT("arch",             "select the instruction architecture",                &arch_var),
+       LC_OPT_ENT_ENUM_INT("opt",              "optimize for instruction architecture",              &opt_arch_var),
+       LC_OPT_ENT_ENUM_INT("fpunit",           "select the floating point unit",                     &fp_unit_var),
+       LC_OPT_ENT_NEGBOOL ("nooptcc",          "do not optimize calling convention",                 &opt_cc),
+       LC_OPT_ENT_BOOL    ("unsafe_floatconv", "do unsafe floating point controlword optimisations", &opt_unsafe_floatconv),
+       LC_OPT_ENT_BOOL    ("machcode",         "output machine code instead of assembler",           &emit_machcode),
        LC_OPT_LAST
 };
 
@@ -740,12 +735,25 @@ typedef union {
 static void x86_cpuid(cpuid_registers *regs, unsigned level)
 {
 #if defined(__GNUC__)
+#      if defined(__PIC__) && !defined(__amd64) // GCC cannot handle EBX in PIC
+       __asm (
+               "pushl %%ebx\n\t"
+               "cpuid\n\t"
+               "movl %%ebx, %1\n\t"
+               "popl %%ebx"
+       : "=a" (regs->r.eax), "=r" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
+       : "a" (level)
+       );
+#      else
        __asm ("cpuid\n\t"
        : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
        : "a" (level)
        );
+#      endif
 #elif defined(_MSC_VER)
        __cpuid(regs->bulk, level);
+#else
+#      error CPUID is missing
 #endif
 }
 
@@ -798,13 +806,11 @@ static void autodetect_arch(void)
        /* We use the cpuid instruction to detect the CPU features */
        if (x86_toogle_cpuid()) {
                cpuid_registers   regs;
-               unsigned          highest_level;
                char              vendorid[13];
                x86_cpu_info_t    cpu_info;
 
                /* get vendor ID */
                x86_cpuid(&regs, 0);
-               highest_level = regs.r.eax;
                memcpy(&vendorid[0], &regs.r.ebx, 4);
                memcpy(&vendorid[4], &regs.r.edx, 4);
                memcpy(&vendorid[8], &regs.r.ecx, 4);
@@ -876,7 +882,8 @@ void ia32_setup_cg_config(void)
        /* P4s don't like inc/decs because they only partially write the flags
         * register which produces false dependencies */
        c->use_incdec           = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
-       c->use_sse2             = use_sse2 && FLAGS(arch, arch_feature_sse2);
+       c->use_softfloat        = FLAGS(fpu_arch, IA32_FPU_ARCH_SOFTFLOAT);
+       c->use_sse2             = FLAGS(fpu_arch, IA32_FPU_ARCH_SSE2) && FLAGS(arch, arch_feature_sse2);
        c->use_ffreep           = FLAGS(opt_arch, arch_athlon_plus);
        c->use_ftst             = !FLAGS(arch, arch_feature_p6_insn);
        /* valgrind can't cope with femms yet and the usefulness of the optimization
@@ -898,7 +905,7 @@ void ia32_setup_cg_config(void)
        c->use_pxor             = FLAGS(opt_arch, arch_netburst);
        c->use_mov_0            = FLAGS(opt_arch, arch_k6) && !opt_size;
        c->use_short_sex_eax    = !FLAGS(opt_arch, arch_k6) && !opt_size;
-       c->use_pad_return       = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
+       c->use_pad_return       = FLAGS(opt_arch, arch_athlon_plus) && !opt_size;
        c->use_bt               = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
        c->use_fisttp           = FLAGS(opt_arch & arch, arch_feature_sse3);
        c->use_sse_prefetch     = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));