change betranshelp semantic to panic instead of duplicating node in case of missing...

[libfirm] / ir / be / ia32 / ia32_architecture.c

diff --git a/ir/be/ia32/ia32_architecture.c b/ir/be/ia32/ia32_architecture.c
index cb729aa..03eabbd 100644 (file)
--- a/ir/be/ia32/ia32_architecture.c
+++ b/ir/be/ia32/ia32_architecture.c
@@ -70,12 +70,18 @@ enum cpu_arch_features {
        arch_feature_3DNow    = 0x00100000, /**< 3DNow! instructions */
        arch_feature_3DNowE   = 0x00200000, /**< Enhanced 3DNow! instructions */
        arch_feature_64bit    = 0x00400000, /**< x86_64 support */
+       arch_feature_sse4_1   = 0x00800000, /**< SSE4.1 instructions */
+       arch_feature_sse4_2   = 0x01000000, /**< SSE4.2 instructions */
+       arch_feature_sse4a    = 0x02000000, /**< SSE4a instructions */
 
        arch_mmx_insn     = arch_feature_mmx,                         /**< MMX instructions */
-       arch_sse1_insn    = arch_feature_sse1  | arch_mmx_insn,       /**< SSE1 instructions, include MMX */
-       arch_sse2_insn    = arch_feature_sse2  | arch_sse1_insn,      /**< SSE2 instructions, include SSE1 */
-       arch_sse3_insn    = arch_feature_sse3  | arch_sse2_insn,      /**< SSE3 instructions, include SSE2 */
-       arch_ssse3_insn   = arch_feature_ssse3 | arch_sse3_insn,      /**< SSSE3 instructions, include SSE3 */
+       arch_sse1_insn    = arch_feature_sse1   | arch_mmx_insn,      /**< SSE1 instructions, include MMX */
+       arch_sse2_insn    = arch_feature_sse2   | arch_sse1_insn,     /**< SSE2 instructions, include SSE1 */
+       arch_sse3_insn    = arch_feature_sse3   | arch_sse2_insn,     /**< SSE3 instructions, include SSE2 */
+       arch_ssse3_insn   = arch_feature_ssse3  | arch_sse3_insn,     /**< SSSE3 instructions, include SSE3 */
+       arch_sse4_1_insn  = arch_feature_sse4_1 | arch_ssse3_insn,    /**< SSE4.1 instructions, include SSSE3 */
+       arch_sse4_2_insn  = arch_feature_sse4_2 | arch_sse4_1_insn,   /**< SSE4.2 instructions, include SSE4.1 */
+       arch_sse4a_insn   = arch_feature_sse4a  | arch_ssse3_insn,    /**< SSE4a instructions, include SSSE3 */
 
        arch_3DNow_insn   = arch_feature_3DNow | arch_feature_mmx,    /**< 3DNow! instructions, including MMX */
        arch_3DNowE_insn  = arch_feature_3DNowE | arch_3DNow_insn,    /**< Enhanced 3DNow! instructions */
@@ -103,16 +109,18 @@ enum cpu_support {
        cpu_prescott    = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
        cpu_nocona      = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
        cpu_core2       = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
+       cpu_penryn      = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
 
        /* AMD CPUs */
        cpu_k6          = arch_k6 | arch_mmx_insn,
        cpu_k6_PLUS     = arch_k6 | arch_3DNow_insn,
        cpu_geode       = arch_geode  | arch_sse1_insn | arch_3DNowE_insn,
+       cpu_athlon_old  = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
        cpu_athlon      = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
        cpu_athlon64    = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
        cpu_k8          = arch_k8  | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
        cpu_k8_sse3     = arch_k8  | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
-       cpu_k10         = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
+       cpu_k10         = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
 
        /* other CPUs */
        cpu_winchip_c6  = arch_i486 | arch_feature_mmx,
@@ -122,6 +130,7 @@ enum cpu_support {
 };
 
 static int         opt_size             = 0;
+static int         emit_machcode        = 0;
 static cpu_support arch                 = cpu_generic;
 static cpu_support opt_arch             = cpu_generic;
 static int         use_sse2             = 0;
@@ -151,12 +160,13 @@ static const lc_opt_enum_int_items_t arch_items[] = {
        { "nocona",       cpu_nocona },
        { "merom",        cpu_core2 },
        { "core2",        cpu_core2 },
+       { "penryn",       cpu_penryn },
 
        { "k6",           cpu_k6 },
        { "k6-2",         cpu_k6_PLUS },
        { "k6-3",         cpu_k6_PLUS },
        { "geode",        cpu_geode },
-       { "athlon",       cpu_athlon },
+       { "athlon",       cpu_athlon_old },
        { "athlon-tbird", cpu_athlon },
        { "athlon-4",     cpu_athlon },
        { "athlon-xp",    cpu_athlon },
@@ -211,6 +221,8 @@ static const lc_opt_table_entry_t ia32_architecture_options[] = {
                          &opt_cc, 1),
        LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
                       "optimisations", &opt_unsafe_floatconv, 1),
+       LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
+                       &emit_machcode),
        LC_OPT_LAST
 };
 
@@ -426,7 +438,8 @@ static void set_arch_costs(void)
 }
 
 /* Evaluate the costs of an instruction. */
-int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
+int ia32_evaluate_insn(insn_kind kind, tarval *tv)
+{
        int cost;
 
        switch (kind) {
@@ -466,11 +479,11 @@ void ia32_setup_cg_config(void)
        set_arch_costs();
 
        c->optimize_size        = opt_size != 0;
-       /* on newer intel cpus mov, pop is often faster then leave although it has a
+       /* on newer intel cpus mov, pop is often faster than leave although it has a
         * longer opcode */
        c->use_leave            = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
        /* P4s don't like inc/decs because they only partially write the flags
-          register which produces false dependencies */
+        * register which produces false dependencies */
        c->use_incdec           = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
        c->use_sse2             = use_sse2 && FLAGS(arch, arch_feature_sse2);
        c->use_ffreep           = FLAGS(opt_arch, arch_athlon_plus);
@@ -493,11 +506,17 @@ void ia32_setup_cg_config(void)
        c->use_imul_mem_imm32   = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
        c->use_pxor             = FLAGS(opt_arch, arch_netburst);
        c->use_mov_0            = FLAGS(opt_arch, arch_k6) && !opt_size;
+       c->use_short_sex_eax    = !FLAGS(opt_arch, arch_k6) && !opt_size;
        c->use_pad_return       = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
        c->use_bt               = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
        c->use_fisttp           = FLAGS(opt_arch & arch, arch_feature_sse3);
+       c->use_sse_prefetch     = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
+       c->use_3dnow_prefetch   = FLAGS(arch, arch_feature_3DNow);
+       c->use_popcnt           = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
+       c->use_i486             = (arch & arch_mask) >= arch_i486;
        c->optimize_cc          = opt_cc;
        c->use_unsafe_floatconv = opt_unsafe_floatconv;
+       c->emit_machcode        = emit_machcode;
 
        c->function_alignment       = arch_costs->function_alignment;
        c->label_alignment          = arch_costs->label_alignment;