#include "set.h"
#include "pdeq.h"
-#include "../be.h"
+#include "be.h"
#include "../bemachine.h"
#include "../beemitter.h"
arch_athlon, /**< Athlon */
arch_athlon_64, /**< Athlon64 */
arch_opteron, /**< Opteron */
+ arch_generic /**< generic */
};
/** checks for l <= x <= h */
/** returns true if it's AMD architecture */
#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
+/** return true if it's a Athlon/Opteron */
+#define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
+
+/** return true if the CPU has MMX support */
+#define ARCH_MMX(x) _IN_RANGE((x), arch_pentium_mmx, arch_opteron)
+
#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
_IN_RANGE((x), arch_athlon, arch_opteron))
fp_sse2 /**< use SSE2 instructions */
};
-/** Sets the used flag to the current floating point architecture. */
-#define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
-
/** Returns non-zero if the current floating point architecture is SSE2. */
#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
/** Returns non-zero if the current floating point architecture is x87. */
#define USE_x87(cg) ((cg)->fp_kind == fp_x87)
-/** Sets the flag to enforce x87 simulation. */
-#define FORCE_x87(cg) ((cg)->force_sim = 1)
-
typedef struct ia32_isa_t ia32_isa_t;
typedef struct ia32_code_gen_t ia32_code_gen_t;
typedef struct ia32_irn_ops_t ia32_irn_ops_t;
int arch; /**< instruction architecture */
int opt_arch; /**< optimize for architecture */
char fp_kind; /**< floating point kind */
- char used_fp; /**< which floating point unit used in this graph */
- char force_sim; /**< set to 1 if x87 simulation should be enforced */
+ char do_x87_sim; /**< set to 1 if x87 simulation should be enforced */
char dump; /**< set to 1 if graphs should be dumped */
ir_node *unknown_gp; /**< unique Unknown_GP node */
ir_node *unknown_vfp; /**< unique Unknown_VFP node */
*/
struct ia32_isa_t {
arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
- be_emit_env_t emit;
pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
+ pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
pmap *types; /**< A map of modes to primitive types */
pmap *tv_ent; /**< A map of entities that store const tarvals */
ia32_optimize_t opt; /**< contains optimization information */
ia32_code_gen_t *cg;
};
+/**
+ * A helper type collecting needed info for IA32 intrinsic lowering.
+ */
struct ia32_intrinsic_env_t {
- ir_graph *irg; /**< the irg, these entities belong to */
- ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
- ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
- ir_entity *ll_d_conv; /**< entity for converts ll -> d */
- ir_entity *d_ll_conv; /**< entity for converts d -> ll */
+ ia32_isa_t *isa; /**< the isa object */
+ ir_graph *irg; /**< the irg, these entities belong to */
+ ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
+ ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
+ ir_entity *ll_d_conv; /**< entity for converts ll -> d */
+ ir_entity *d_ll_conv; /**< entity for converts d -> ll */
+ ir_entity *divdi3; /**< entity for __divdi3 library call */
+ ir_entity *moddi3; /**< entity for __moddi3 library call */
+ ir_entity *udivdi3; /**< entity for __udivdi3 library call */
+ ir_entity *umoddi3; /**< entity for __umoddi3 library call */
+ tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */
};
-/** mode for the floating point control word */
+/** The mode for the floating point control word. */
extern ir_mode *mode_fpcw;
+/** The current code generator. */
+extern ia32_code_gen_t *ia32_current_cg;
+
/**
* Returns the unique per irg GP NoReg node.
*/
ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
/**
- * Returns the uniqure per irg FPU truncation mode node.
+ * Returns the unique per irg FPU truncation mode node.
*/
ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);