get rid of benodesets (in favour of ir_nodeset), report nextuse place in beuses

[libfirm] / ir / be / ia32 / bearch_ia32_t.h

diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h
index 98852b6..e7327c9 100644 (file)
--- a/ir/be/ia32/bearch_ia32_t.h
+++ b/ir/be/ia32/bearch_ia32_t.h
@@ -49,67 +49,6 @@ typedef enum ia32_optimize_t ia32_optimize_t;
 typedef enum cpu_support     cpu_support;
 typedef enum fp_support      fp_support;
 
-/**
- * Bitmask for the backend optimization settings.
- */
-enum ia32_optimize_t {
-       IA32_OPT_INCDEC    = 1 << 0,   /**< optimize add/sub 1/-1 to inc/dec */
-       IA32_OPT_CC        = 1 << 1,
-};
-
-/**
- * Architectures. Clustered for easier macro implementation,
- * do not change.
- */
-enum cpu_support {
-       arch_i386,          /**< i386 */
-       arch_i486,          /**< i486 */
-       arch_pentium,       /**< Pentium */
-       arch_pentium_pro,   /**< Pentium Pro */
-       arch_pentium_mmx,   /**< Pentium MMX */
-       arch_pentium_2,     /**< Pentium II */
-       arch_pentium_3,     /**< Pentium III */
-       arch_pentium_4,     /**< Pentium IV */
-       arch_pentium_m,     /**< Pentium M */
-       arch_core,          /**< Core */
-       arch_k6,            /**< K6 */
-       arch_athlon,        /**< Athlon */
-       arch_athlon_64,     /**< Athlon64 */
-       arch_opteron,       /**< Opteron */
-       arch_generic        /**< generic */
-};
-
-/** checks for l <= x <= h */
-#define _IN_RANGE(x, l, h)  ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
-
-/** returns true if it's Intel architecture */
-#define ARCH_INTEL(x)       _IN_RANGE((x), arch_i386, arch_core)
-
-/** returns true if it's AMD architecture */
-#define ARCH_AMD(x)         _IN_RANGE((x), arch_k6, arch_opteron)
-
-/** return true if it's a Athlon/Opteron */
-#define ARCH_ATHLON(x)      _IN_RANGE((x), arch_athlon, arch_opteron)
-
-/** return true if the CPU has MMX support */
-#define ARCH_MMX(x)         _IN_RANGE((x), arch_pentium_mmx, arch_opteron)
-
-#define IS_P6_ARCH(x)       (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
-                             _IN_RANGE((x), arch_athlon, arch_opteron))
-
-/** floating point support */
-enum fp_support {
-       fp_none,  /**< no floating point instructions are used */
-       fp_x87,   /**< use x87 instructions */
-       fp_sse2   /**< use SSE2 instructions */
-};
-
-/** Returns non-zero if the current floating point architecture is SSE2. */
-#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
-
-/** Returns non-zero if the current floating point architecture is x87. */
-#define USE_x87(cg)  ((cg)->fp_kind == fp_x87)
-
 typedef struct ia32_isa_t            ia32_isa_t;
 typedef struct ia32_code_gen_t       ia32_code_gen_t;
 typedef struct ia32_irn_ops_t        ia32_irn_ops_t;
@@ -126,10 +65,6 @@ struct ia32_code_gen_t {
        ia32_isa_t                     *isa;           /**< for fast access to the isa object */
        be_irg_t                       *birg;          /**< The be-irg (contains additional information about the irg) */
        ir_node                        **blk_sched;    /**< an array containing the scheduled blocks */
-       ia32_optimize_t                opt;            /**< contains optimization information */
-       int                            arch;           /**< instruction architecture */
-       int                            opt_arch;       /**< optimize for architecture */
-       char                           fp_kind;        /**< floating point kind */
        char                           do_x87_sim;     /**< set to 1 if x87 simulation should be enforced */
        char                           dump;           /**< set to 1 if graphs should be dumped */
        ir_node                       *unknown_gp;     /**< unique Unknown_GP node */
@@ -154,10 +89,6 @@ struct ia32_isa_t {
        pmap                  *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
        pmap                  *types;         /**< A map of modes to primitive types */
        pmap                  *tv_ent;        /**< A map of entities that store const tarvals */
-       ia32_optimize_t       opt;            /**< contains optimization information */
-       int                   arch;           /**< instruction architecture */
-       int                   opt_arch;       /**< optimize for architecture */
-       int                   fp_kind;        /**< floating point kind */
        ia32_code_gen_t       *cg;            /**< the current code generator */
        const be_machine_t    *cpu;           /**< the abstract machine */
 #ifndef NDEBUG
@@ -208,11 +139,6 @@ ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
 
-/**
- * Returns the unique per irg FP NoReg node.
- */
-ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
-
 /**
  * Returns the unique per irg FPU truncation mode node.
  */