-#ifndef _BEARCH_IA32_T_H_
-#define _BEARCH_IA32_T_H_
+/*
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
-#include "firm_config.h"
+/**
+ * @file
+ * @brief This is the main ia32 firm backend driver.
+ * @author Christian Wuerdig
+ */
+#ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
+#define FIRM_BE_IA32_BEARCH_IA32_T_H
+#include "config.h"
#include "pmap.h"
#include "debug.h"
-#include "bearch_ia32.h"
#include "ia32_nodes_attr.h"
#include "set.h"
-#include "../be.h"
+#include "pdeq.h"
+
+#include "be.h"
+#include "beemitter.h"
+#include "gen_ia32_regalloc_if.h"
#ifdef NDEBUG
#define SET_IA32_ORIG_NODE(n, o)
-#else
-#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
+#else /* ! NDEBUG */
+#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o)
#endif /* NDEBUG */
-/* some typedefs */
+typedef struct ia32_isa_t ia32_isa_t;
+typedef struct ia32_irn_ops_t ia32_irn_ops_t;
+typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
+
+typedef struct ia32_irg_data_t {
+ ir_node **blk_sched; /**< an array containing the scheduled blocks */
+ unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */
+ unsigned dump:1; /**< set to 1 if graphs should be dumped */
+ ir_node *noreg_gp; /**< unique NoReg_GP node */
+ ir_node *noreg_vfp; /**< unique NoReg_VFP node */
+ ir_node *noreg_xmm; /**< unique NoReg_XMM node */
+
+ ir_node *fpu_trunc_mode; /**< truncate fpu mode */
+ ir_node *get_eip; /**< get eip node */
+} ia32_irg_data_t;
/**
- * Bitmask for the backend optimization settings.
+ * IA32 ISA object
*/
-typedef enum _ia32_optimize_t {
- IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
- IA32_OPT_DOAM = 2, /**< do address mode optimizations */
- IA32_OPT_LEA = 4, /**< optimize address caluclations into LEAs */
- IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
- IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
- IA32_OPT_EXTBB = 32, /**< do extended basic block scheduling */
-} ia32_optimize_t;
+struct ia32_isa_t {
+ arch_env_t base; /**< must be derived from arch_env_t */
+ pmap *tv_ent; /**< A map of entities that store const tarvals */
+ int fpu_arch; /**< FPU architecture */
+};
/**
- * Architectures. Clustered for easier macro implementation,
- * do not change.
+ * A helper type collecting needed info for IA32 intrinsic lowering.
*/
-typedef enum cpu_support {
- arch_i386, /**< i386 */
- arch_i486, /**< i486 */
- arch_pentium, /**< Pentium */
- arch_pentium_pro, /**< Pentium Pro */
- arch_pentium_mmx, /**< Pentium MMX */
- arch_pentium_2, /**< Pentium II */
- arch_pentium_3, /**< Pentium III */
- arch_pentium_4, /**< Pentium IV */
- arch_pentium_m, /**< Pentium M */
- arch_core, /**< Core */
- arch_k6, /**< K6 */
- arch_athlon, /**< Athlon */
- arch_athlon_64, /**< Athlon64 */
- arch_opteron, /**< Opteron */
-} cpu_support;
-
-/** checks for l <= x <= h */
-#define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
-
-/** returns true if it's Intel architecture */
-#define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
-
-/** returns true if it's AMD architecture */
-#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
-
-#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
- _IN_RANGE((x), arch_athlon, arch_opteron))
-
-/** floating point support */
-typedef enum fp_support {
- fp_none, /**< no floating point instructions are used */
- fp_x87, /**< use x87 instructions */
- fp_sse2 /**< use SSE2 instructions */
-} fp_support;
-
-/** Sets the used flag to the current floating point architecture. */
-#define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
-
-/** Returns non-zero if the current floating point architecture is SSE2. */
-#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
-
-/** Returns non-zero if the current floating point architecture is x87. */
-#define USE_x87(cg) ((cg)->fp_kind == fp_x87)
-
-typedef struct _ia32_isa_t ia32_isa_t;
+struct ia32_intrinsic_env_t {
+ ia32_isa_t *isa; /**< the isa object */
+ ir_graph *irg; /**< the irg, these entities belong to */
+ ir_entity *divdi3; /**< entity for __divdi3 library call */
+ ir_entity *moddi3; /**< entity for __moddi3 library call */
+ ir_entity *udivdi3; /**< entity for __udivdi3 library call */
+ ir_entity *umoddi3; /**< entity for __umoddi3 library call */
+};
+
+typedef enum transformer_t {
+ TRANSFORMER_DEFAULT,
+#ifdef FIRM_GRGEN_BE
+ TRANSFORMER_PBQP,
+ TRANSFORMER_RAND
+#endif
+} transformer_t;
+
+#ifdef FIRM_GRGEN_BE
+/** The selected transformer. */
+extern transformer_t be_transformer;
+
+#else
+#define be_transformer TRANSFORMER_DEFAULT
+#endif
+
+/** The mode for the floating point control word. */
+extern ir_mode *ia32_mode_fpcw;
+/** extended floatingpoint mode */
+extern ir_mode *ia32_mode_E;
+extern ir_type *ia32_type_E;
+
+static inline ia32_irg_data_t *ia32_get_irg_data(const ir_graph *irg)
+{
+ return (ia32_irg_data_t*) be_birg_from_irg(irg)->isa_link;
+}
/**
- * IA32 code generator
+ * Returns the unique per irg GP NoReg node.
*/
-typedef struct _ia32_code_gen_t {
- const arch_code_generator_if_t *impl; /**< implementation */
- ir_graph *irg; /**< current irg */
- const arch_env_t *arch_env; /**< the arch env */
- set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
- ia32_isa_t *isa; /**< for fast access to the isa object */
- const be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
- ir_node **blk_sched; /**< an array containing the scheduled blocks */
- ia32_optimize_t opt; /**< contains optimization information */
- entity *fp_to_gp; /**< allocated entity for fp to gp conversion */
- entity *gp_to_fp; /**< allocated entity for gp to fp conversion */
- int arch; /**< instruction architecture */
- int opt_arch; /**< optimize for architecture */
- int fp_kind; /**< floating point kind */
- char used_fp; /**< which floating point unit used in this graph */
- DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
-} ia32_code_gen_t;
+ir_node *ia32_new_NoReg_gp(ir_graph *irg);
+ir_node *ia32_new_NoReg_xmm(ir_graph *irg);
+ir_node *ia32_new_NoReg_vfp(ir_graph *irg);
/**
- * IA32 ISA object
+ * Returns the unique per irg FPU truncation mode node.
*/
-struct _ia32_isa_t {
- arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
- pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
- pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
- pmap *types; /**< A map of modes to primitive types */
- pmap *tv_ent; /**< A map of entities that store const tarvals */
- ia32_optimize_t opt; /**< contains optimization information */
- int arch; /**< instruction architecture */
- int opt_arch; /**< optimize for architecture */
- int fp_kind; /**< floating point kind */
- ia32_code_gen_t *cg; /**< the current code generator */
- FILE *out; /**< output file */
-#ifndef NDEBUG
- struct obstack *name_obst; /**< holds the original node names (for debugging) */
- unsigned long name_obst_size;
-#endif /* NDEBUG */
-};
+ir_node *ia32_new_Fpu_truncate(ir_graph *irg);
-typedef struct _ia32_irn_ops_t {
- const arch_irn_ops_if_t *impl;
- ia32_code_gen_t *cg;
-} ia32_irn_ops_t;
-
-/* this is a struct to minimize the number of parameters
- for transformation walker */
-typedef struct _ia32_transform_env_t {
- dbg_info *dbg; /**< The node debug info */
- ir_graph *irg; /**< The irg, the node should be created in */
- ir_node *block; /**< The block, the node should belong to */
- ir_node *irn; /**< The irn, to be transformed */
- ir_mode *mode; /**< The mode of the irn */
- ia32_code_gen_t *cg; /**< The code generator */
- DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
-} ia32_transform_env_t;
+/**
+ * Split instruction with source AM into Load and separate instruction.
+ * @return result of the Load
+ */
+ir_node *ia32_turn_back_am(ir_node *node);
+
+/**
+ * Maps all intrinsic calls that the backend support
+ * and map all instructions the backend did not support
+ * to runtime calls.
+ */
+void ia32_handle_intrinsics(void);
+
+/**
+ * Ia32 implementation.
+ *
+ * @param method the method type of the emulation function entity
+ * @param op the emulated ir_op
+ * @param imode the input mode of the emulated opcode
+ * @param omode the output mode of the emulated opcode
+ * @param context the context parameter
+ */
+ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
+ const ir_mode *imode, const ir_mode *omode,
+ void *context);
/**
- * Creates the unique per irg GP NoReg node.
+ * Return the stack entity that contains the return address.
*/
-ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
+ir_entity *ia32_get_return_address_entity(ir_graph *irg);
/**
- * Creates the unique per irg FP NoReg node.
+ * Return the stack entity that contains the frame address.
*/
-ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
+ir_entity *ia32_get_frame_address_entity(ir_graph *irg);
-#endif /* _BEARCH_IA32_T_H_ */
+#endif
projects / libfirm / blobdiff