#ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
#define FIRM_BE_IA32_BEARCH_IA32_T_H
-#include "firm_config.h"
-
#include "pmap.h"
#include "debug.h"
#include "ia32_nodes_attr.h"
struct ia32_code_gen_t {
const arch_code_generator_if_t *impl; /**< implementation */
ir_graph *irg; /**< current irg */
- const arch_env_t *arch_env; /**< the arch env */
set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
ia32_isa_t *isa; /**< for fast access to the isa object */
be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
* IA32 ISA object
*/
struct ia32_isa_t {
- arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
+ arch_env_t arch_env; /**< must be derived from arch_env_t */
pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */
};
+typedef enum transformer_t {
+ TRANSFORMER_DEFAULT,
+#ifdef FIRM_GRGEN_BE
+ TRANSFORMER_PBQP,
+ TRANSFORMER_RAND
+#endif
+} transformer_t;
+
+/** The selected transformer. */
+extern transformer_t be_transformer;
+
/** The mode for the floating point control word. */
extern ir_mode *mode_fpcw;
ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
/**
- * Returns gp_noreg or fp_noreg, depending on input requirements.
+ * Split instruction with source AM into Load and separate instruction.
+ * @return result of the Load
*/
-ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
+ir_node *turn_back_am(ir_node *node);
/**
* Maps all intrinsic calls that the backend support