Marginally reduce the number of calls to arch_get_irn_reg_class().

[libfirm] / ir / be / ia32 / bearch_ia32_t.h

diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h
index 8cafc1f..4f8889d 100644 (file)
--- a/ir/be/ia32/bearch_ia32_t.h
+++ b/ir/be/ia32/bearch_ia32_t.h
@@ -26,8 +26,7 @@
 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
 #define FIRM_BE_IA32_BEARCH_IA32_T_H
 
-#include "firm_config.h"
-
+#include "config.h"
 #include "pmap.h"
 #include "debug.h"
 #include "ia32_nodes_attr.h"
@@ -60,7 +59,6 @@ typedef struct ia32_intrinsic_env_t  ia32_intrinsic_env_t;
 struct ia32_code_gen_t {
        const arch_code_generator_if_t *impl;          /**< implementation */
        ir_graph                       *irg;           /**< current irg */
-       const arch_env_t               *arch_env;      /**< the arch env */
        set                            *reg_set;       /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
        ia32_isa_t                     *isa;           /**< for fast access to the isa object */
        be_irg_t                       *birg;          /**< The be-irg (contains additional information about the irg) */
@@ -123,9 +121,14 @@ typedef enum transformer_t {
 #endif
 } transformer_t;
 
+#ifdef FIRM_GRGEN_BE
 /** The selected transformer. */
 extern transformer_t be_transformer;
 
+#else
+#define be_transformer TRANSFORMER_DEFAULT
+#endif
+
 /** The mode for the floating point control word. */
 extern ir_mode *mode_fpcw;
 
@@ -152,6 +155,12 @@ ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
  */
 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
 
+/**
+ * Split instruction with source AM into Load and separate instruction.
+ * @return result of the Load
+ */
+ir_node *turn_back_am(ir_node *node);
+
 /**
  * Maps all intrinsic calls that the backend support
  * and map all instructions the backend did not support