}
}
-/**************************************************
- * _ _ _ __
- * | | | (_)/ _|
- * _ __ ___ __ _ __ _| | | ___ ___ _| |_
- * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
- * | | | __/ (_| | | (_| | | | (_) | (__ | | |
- * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
- * __/ |
- * |___/
- **************************************************/
static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
const ir_node *node, int pos)
return;
if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
- ia32_code_gen_t *cg = ia32_current_cg;
- int omit_fp = be_abi_omit_fp(cg->birg->abi);
- if (omit_fp) {
+ ir_graph *irg = get_irn_irg(irn);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ if (layout->sp_relative) {
/* Pop nodes modify the stack pointer before calculating the
* destination address, so fix this here
*/
ia32_perform_memory_operand,
};
-/**************************************************
- * _ _ __
- * | | (_)/ _|
- * ___ ___ __| | ___ __ _ ___ _ __ _| |_
- * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
- * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
- * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
- * __/ |
- * |___/
- **************************************************/
static ir_entity *mcount = NULL;
ia32_setup_fpu_mode(cg);
/* fixup flags */
- be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
+ be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
&flags_remat);
ia32_add_missing_keeps(cg);
static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
{
ir_node *block = get_nodes_block(node);
- ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
+ ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
int arity = be_get_MemPerm_entity_arity(node);
ir_node **pops = ALLOCAN(ir_node*, arity);
ir_node *in[1];
{
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
/* create and coalesce frame entities */
irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
/* we might have to rewrite x87 virtual registers */
if (cg->do_x87_sim) {
- x87_simulate_graph(cg->birg);
+ x87_simulate_graph(cg->irg);
}
/* do peephole optimisations */
return get_eip;
}
-static void *ia32_cg_init(be_irg_t *birg);
+static void *ia32_cg_init(ir_graph *irg);
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
/**
* Initializes a IA32 code generator.
*/
-static void *ia32_cg_init(be_irg_t *birg)
+static void *ia32_cg_init(ir_graph *irg)
{
- ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
+ ia32_isa_t *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
cg->impl = &ia32_code_gen_if;
- cg->irg = birg->irg;
+ cg->irg = irg;
cg->isa = isa;
- cg->birg = birg;
cg->blk_sched = NULL;
- cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
+ cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
+ cg->gprof = (be_get_irg_options(irg)->gprof) ? 1 : 0;
if (cg->gprof) {
/* Linux gprof implementation needs base pointer */
- birg->main_env->options->omit_fp = 0;
+ be_get_irg_options(irg)->omit_fp = 0;
}
/* enter it */
}
-
-/*****************************************************************
- * ____ _ _ _____ _____
- * | _ \ | | | | |_ _|/ ____| /\
- * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
- * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
- * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
- * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
- *
- *****************************************************************/
-
/**
* Set output modes for GCC
*/
NULL, /* main environment */
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
+ false, /* no custom abi handling */
},
NULL, /* 16bit register names */
NULL, /* 8bit register names */