#include "instrument.h"
#include "iropt_t.h"
#include "lower_dw.h"
-
-#include "../beabi.h"
-#include "../beirg.h"
-#include "../benode.h"
-#include "../belower.h"
-#include "../besched.h"
+#include "lower_calls.h"
+#include "lower_mode_b.h"
+#include "lower_softfloat.h"
+
+#include "beabi.h"
+#include "beirg.h"
+#include "benode.h"
+#include "belower.h"
+#include "besched.h"
#include "be.h"
-#include "../be_t.h"
-#include "../beirgmod.h"
-#include "../be_dbgout.h"
-#include "../beblocksched.h"
-#include "../bemachine.h"
-#include "../bespillslots.h"
-#include "../bemodule.h"
-#include "../begnuas.h"
-#include "../bestate.h"
-#include "../beflags.h"
-#include "../betranshlp.h"
-#include "../belistsched.h"
-#include "../beabihelper.h"
+#include "be_t.h"
+#include "beirgmod.h"
+#include "be_dbgout.h"
+#include "beblocksched.h"
+#include "bemachine.h"
+#include "bespillutil.h"
+#include "bespillslots.h"
+#include "bemodule.h"
+#include "begnuas.h"
+#include "bestate.h"
+#include "beflags.h"
+#include "betranshlp.h"
+#include "belistsched.h"
+#include "beabihelper.h"
+#include "bestack.h"
#include "bearch_ia32_t.h"
transformer_t be_transformer = TRANSFORMER_DEFAULT;
#endif
-DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-
-ir_mode *ia32_mode_fpcw = NULL;
+ir_mode *ia32_mode_fpcw;
+ir_mode *ia32_mode_E;
+ir_type *ia32_type_E;
/** The current omit-fp state */
static ir_type *omit_fp_between_type = NULL;
};
-typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
+typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
/**
* Used to create per-graph unique pseudo nodes.
static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
{
ir_graph *irg = get_irn_irg(irn);
- const arch_register_req_t *req = arch_get_register_req(irn, pos);
+ const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
assert(req != NULL && "Missing register requirements");
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
- dbg_info *dbg;
+ dbg_info *dbgi;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
nomem = get_irg_no_mem(irg);
- dbg = get_irn_dbg_info(irn);
+ dbgi = get_irn_dbg_info(irn);
/* initialize structure */
inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
break;
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
if (i == n_ia32_binary_left) {
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
case iro_ia32_Xor:
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
/* we can't swap left/right for limited registers
* (As this (currently) breaks constraint handling copies)
*/
- req = arch_get_in_register_req(irn, n_ia32_binary_left);
+ req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
if (req->type & arch_register_req_type_limited)
return 0;
break;
/* do local optimizations (mainly CSE) */
optimize_graph_df(irg);
+ /* backend code expects that outedges are always enabled */
+ edges_assure(irg);
if (irg_data->dump)
dump_ir_graph(irg, "transformed");
/* do code placement, to optimize the position of constants */
place_code(irg);
+ /* backend code expects that outedges are always enabled */
+ edges_assure(irg);
if (irg_data->dump)
dump_ir_graph(irg, "place");
ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
ir_node *base = get_irn_n(node, n_ia32_base);
- ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
ir_node *mem = get_irn_n(node, n_ia32_mem);
ir_node *noreg;
- ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
+ ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
case ia32_AddrModeD:
/* TODO implement this later... */
panic("found DestAM with flag user %+F this should not happen", node);
- break;
default: assert(type == ia32_Normal); break;
}
static void transform_to_Load(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(spillmode)) {
if (ia32_cg_config.use_sse2)
- new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
- new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
}
else
- new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, spillmode);
DBG_OPT_RELOAD2LD(node, new_op);
- proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
+ proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
static void transform_to_Store(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
- store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
} else {
- store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
+ store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
}
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
- store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
- store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_graph *irg = get_irn_irg(node);
- ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *frame = get_irg_frame(irg);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
+ ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_irn_irg(node);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg,
+ ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
get_irg_no_mem(irg), sp);
set_ia32_frame_ent(pop, ent);
static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_mode *spmode = mode_Iu;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *spmode = mode_Iu;
const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
- sp = new_rd_Proj(dbg, pred, spmode, pos);
+ sp = new_rd_Proj(dbgi, pred, spmode, pos);
arch_set_irn_register(sp, spreg);
return sp;
sched_add_after(start, push);
/* move esp to ebp */
- curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
+ curr_bp = be_new_Copy(block, curr_sp);
sched_add_after(push, curr_bp);
be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
- curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
+ curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
sched_add_after(curr_bp, curr_sp);
be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
edges_reroute(initial_bp, curr_bp);
set_irn_n(push, n_ia32_Push_stack, initial_sp);
sched_add_after(curr_sp, incsp);
+ /* make sure the initial IncSP is really used by someone */
+ if (get_irn_n_edges(incsp) <= 1) {
+ ir_node *in[] = { incsp };
+ ir_node *keep = be_new_Keep(block, 1, in);
+ sched_add_after(incsp, keep);
+ }
+
layout->initial_bias = -4;
} else {
ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
}
/**
- * We transform Spill and Reload here. This needs to be done before
- * stack biasing otherwise we would miss the corrected offset for these nodes.
+ * Last touchups for the graph before emit: x87 simulation to replace the
+ * virtual with real x87 instructions, creating a block schedule and peephole
+ * optimisations.
*/
-static void ia32_after_ra(ir_graph *irg)
+static void ia32_finish(ir_graph *irg)
{
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
bool at_begin = stack_layout->sp_relative ? true : false;
be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
introduce_prolog_epilog(irg);
-}
-/**
- * Last touchups for the graph before emit: x87 simulation to replace the
- * virtual with real x87 instructions, creating a block schedule and peephole
- * optimisations.
- */
-static void ia32_finish(ir_graph *irg)
-{
- ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ /* fix stack entity offsets */
+ be_abi_fix_stack_nodes(irg);
+ be_abi_fix_stack_bias(irg);
+ /* fix 2-address code constraints */
ia32_finish_irg(irg);
/* we might have to rewrite x87 virtual registers */
/* do peephole optimisations */
ia32_peephole_optimization(irg);
+ be_remove_dead_nodes_from_schedule(irg);
+
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
irg_data->blk_sched = be_create_block_schedule(irg);
5, /* costs for a reload instruction */
false, /* no custom abi handling */
},
- NULL, /* types */
NULL, /* tv_ents */
NULL, /* abstract machine */
+ IA32_FPU_ARCH_X87, /* FPU architecture */
};
static void init_asm_constraints(void)
*isa = ia32_isa_template;
if (ia32_mode_fpcw == NULL) {
- ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
}
ia32_register_init();
ia32_create_opcodes(&ia32_irn_ops);
be_emit_init(file_handle);
- isa->types = pmap_create();
isa->tv_ent = pmap_create();
isa->cpu = ia32_init_machine_description();
be_gas_emit_decls(isa->base.main_env);
pmap_destroy(isa->tv_ent);
- pmap_destroy(isa->types);
be_emit_exit();
static void ia32_get_call_abi(const void *self, ir_type *method_type,
be_abi_call_t *abi)
{
- ir_type *tp;
- ir_mode *mode;
unsigned cc;
int n, i, regnum;
int pop_amount = 0;
(void) self;
/* set abi flags for calls */
- call_flags.bits.left_to_right = 0; /* always last arg first on stack */
call_flags.bits.store_args_sequential = 0;
/* call_flags.bits.try_omit_fp not changed: can handle both settings */
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- ir_mode *mode;
- const arch_register_t *reg = NULL;
+ const arch_register_t *reg = NULL;
+ ir_type *tp = get_method_param_type(method_type, i);
+ ir_mode *mode = get_type_mode(tp);
- tp = get_method_param_type(method_type, i);
- mode = get_type_mode(tp);
if (mode != NULL) {
reg = ia32_get_RegParam_reg(cc, regnum, mode);
}
/* In case of 64bit returns, we will have two 32bit values */
if (n == 2) {
- tp = get_method_res_type(method_type, 0);
- mode = get_type_mode(tp);
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
assert(!mode_is_float(mode) && "two FP results not supported");
be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
}
else if (n == 1) {
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
const arch_register_t *reg;
-
- tp = get_method_res_type(method_type, 0);
assert(is_atomic_type(tp));
- mode = get_type_mode(tp);
reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
{
ir_mode *mode;
+ /* middleend can handle some things */
+ if (ir_is_optimizable_mux(sel, mux_false, mux_true))
+ return true;
/* we can handle Set for all modes and compares */
if (mux_is_set(sel, mux_true, mux_false))
return true;
if (get_mode_size_bits(mode) > 32)
return false;
/* we can handle Abs for all modes and compares (except 64bit) */
- if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
+ if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
return true;
/* we can't handle MuxF yet */
if (mode_is_float(mode))
return ia32_get_clobber_register(clobber) != NULL;
}
-static ir_node *ia32_create_set(ir_node *cond)
-{
- /* ia32-set function produces 8-bit results which have to be converted */
- ir_node *set = ir_create_mux_set(cond, mode_Bu);
- ir_node *block = get_nodes_block(set);
- return new_r_Conv(block, set, mode_Iu);
-}
-
static void ia32_lower_for_target(void)
{
size_t i, n_irgs = get_irp_n_irgs();
- lower_mode_b_config_t lower_mode_b_config = {
- mode_Iu, /* lowered mode */
- ia32_create_set,
- 0, /* don't lower direct compares */
- };
- lower_params_t params = {
- 4, /* def_ptr_alignment */
- LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
- ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
- NULL, /* find pointer type */
- NULL, /* ret_compound_in_regs */
- };
/* perform doubleword lowering */
lwrdw_param_t lower_dw_params = {
&intrinsic_env,
};
- /* lower compound param handling */
- lower_calls_with_compounds(¶ms);
+ ia32_create_opcodes(&ia32_irn_ops);
+
+ /* lower compound param handling
+ * Note: we lower compound arguments ourself, since on ia32 we don't
+ * have hidden parameters but know where to find the structs on the stack.
+ * (This also forces us to always allocate space for the compound arguments
+ * on the callframe and we can't just use an arbitrary position on the
+ * stackframe)
+ */
+ lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
+
+ /* replace floating point operations by function calls */
+ if (ia32_cg_config.use_softfloat) {
+ lower_floating_point();
+ }
ir_prepare_dw_lowering(&lower_dw_params);
ir_lower_dw_ops();
for (i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
/* lower for mode_b stuff */
- ir_lower_mode_b(irg, &lower_mode_b_config);
+ ir_lower_mode_b(irg, mode_Iu);
/* break up switches with wide ranges */
lower_switch(irg, 4, 256, false);
}
+
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
+ * so we can generate rep movs later, and turn all big CopyBs into
+ * memcpy calls. */
+ lower_CopyB(irg, 64, 8193, true);
+ }
}
/**
*/
static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
{
- ir_graph *irg = get_irn_irg(block);
- ir_node *p = trampoline;
- ir_mode *mode = get_irn_mode(p);
- ir_node *st;
+ ir_graph *const irg = get_irn_irg(block);
+ ir_node * p = trampoline;
+ ir_mode *const mode = get_irn_mode(p);
+ ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
+ ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
+ ir_node * st;
/* mov ecx,<env> */
st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ p = new_r_Add(block, p, one, mode);
st = new_r_Store(block, mem, p, env, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
+ p = new_r_Add(block, p, four, mode);
/* jmp <callee> */
st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ p = new_r_Add(block, p, one, mode);
st = new_r_Store(block, mem, p, callee, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
+ p = new_r_Add(block, p, four, mode);
return mem;
}
1, /* support inline assembly */
1, /* support Rotl nodes */
0, /* little endian */
- NULL, /* will be set later */
+ 1, /* modulo shift efficient */
+ 0, /* non-modulo shift not efficient */
+ &ad, /* will be set later */
ia32_is_mux_allowed,
+ 32, /* machine_size */
NULL, /* float arithmetic mode, will be set below */
+ NULL, /* long long type */
+ NULL, /* unsigned long long type */
+ NULL, /* long double type */
12, /* size of trampoline code */
4, /* alignment of trampoline code */
ia32_create_trampoline_fkt,
4 /* alignment of stack parameter */
};
+ if (ia32_mode_E == NULL) {
+ /* note mantissa is 64bit but with explicitely encoded 1 so the really
+ * usable part as counted by firm is only 63 bits */
+ ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
+ ia32_type_E = new_type_primitive(ia32_mode_E);
+ set_type_size_bytes(ia32_type_E, 12);
+ set_type_alignment_bytes(ia32_type_E, 16);
+ }
+
+ ir_mode *mode_long_long
+ = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
+ ir_type *type_long_long = new_type_primitive(mode_long_long);
+ ir_mode *mode_unsigned_long_long
+ = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
+ ir_type *type_unsigned_long_long
+ = new_type_primitive(mode_unsigned_long_long);
+
ia32_setup_cg_config();
/* doesn't really belong here, but this is the earliest place the backend
* is called... */
init_asm_constraints();
- p.dep_param = &ad;
- if (! ia32_cg_config.use_sse2)
- p.mode_float_arithmetic = mode_E;
+ p.type_long_long = type_long_long;
+ p.type_unsigned_long_long = type_unsigned_long_long;
+
+ if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
+ p.mode_float_arithmetic = NULL;
+ p.type_long_double = NULL;
+ } else {
+ p.mode_float_arithmetic = ia32_mode_E;
+ p.type_long_double = ia32_type_E;
+ }
return &p;
}
ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
ia32_before_ra, /* before register allocation hook */
- ia32_after_ra, /* after register allocation hook */
ia32_finish, /* called before codegen */
ia32_emit, /* emit && done */
ia32_register_saved_by,
+ be_new_spill,
+ be_new_reload
};
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
-
ia32_init_emitter();
ia32_init_finish();
ia32_init_optimize();
projects / libfirm / blobdiff