#include "bitset.h"
#include "debug.h"
-#include "../bearch.h" /* the general register allocator interface */
+#include "../beabi.h" /* the general register allocator interface */
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
#undef is_Start
#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
+ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
+ if (! cg->noreg_gp) {
+ cg->noreg_gp = be_new_NoReg(&ia32_gp_regs[REG_XXX], cg->irg, get_irg_start_block(cg->irg));
+ }
+
+ return cg->noreg_gp;
+}
+
+ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
+ if (! cg->noreg_fp) {
+ cg->noreg_fp = be_new_NoReg(&ia32_fp_regs[REG_XXXX], cg->irg, get_irg_start_block(cg->irg));
+ }
+
+ return cg->noreg_fp;
+}
+
/**************************************************
* _ _ _ __
* | | | (_)/ _|
return req;
}
else if (is_Start_Proj(irn)) {
- irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
+/* irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
assert(irn_req && "missing requirement for regparam");
- memcpy(req, &(irn_req->req), sizeof(*req));
+ memcpy(req, &(irn_req->req), sizeof(*req)); */
+ memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
return req;
+ //return NULL;
}
else if (is_Proj(irn)) {
if (pos == -1) {
memcpy(req, &(irn_req->req), sizeof(*req));
- if (arch_register_req_is(&(irn_req->req), should_be_same) ||
- arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
- req->other = get_irn_n(irn, irn_req->pos);
+ if (arch_register_req_is(&(irn_req->req), should_be_same)) {
+ assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
+ req->other_same = get_irn_n(irn, irn_req->same_pos);
+ }
+
+ if (arch_register_req_is(&(irn_req->req), should_be_different)) {
+ assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
+ req->other_different = get_irn_n(irn, irn_req->different_pos);
}
}
else {
if (is_Phi(irn)) {
DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
if (mode_is_float(mode))
- memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
else if (mode_is_int(mode) || mode_is_reference(mode))
- memcpy(req, &(ia32_default_req_ia32_general_purpose.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
else if (mode == mode_T || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
return NULL;
}
else if (get_irn_op(irn) == op_Return && pos > 0) {
DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
- memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_gp_eax.req), sizeof(*req));
}
else {
DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
int pos = 0;
- if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
- is_P_frame_base_Proj(irn) ||
- is_Start_Proj(irn))
- {
- /* don't skip the proj, we want to take the else below */
- }
- else if (is_Proj(irn)) {
+ if (is_Proj(irn)) {
pos = ia32_translate_proj_pos(irn);
irn = my_skip_proj(irn);
}
int pos = 0;
const arch_register_t *reg = NULL;
- if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
- is_P_frame_base_Proj(irn) ||
- is_Start_Proj(irn))
- {
- /* don't skip the proj, we want to take the else below */
- }
- else if (is_Proj(irn)) {
+ if (is_Proj(irn)) {
pos = ia32_translate_proj_pos(irn);
irn = my_skip_proj(irn);
}
if (is_ia32_irn(irn))
return get_ia32_flags(irn);
else {
- if (is_Start_Proj(irn))
- return arch_irn_flags_ignore;
-
return 0;
}
}
+static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
+ if (get_ia32_use_frame(irn)) {
+ /* TODO: correct offset */
+ }
+}
+
/* fill register allocator interface */
static const arch_irn_ops_if_t ia32_irn_ops_if = {
ia32_set_irn_reg,
ia32_get_irn_reg,
ia32_classify,
- ia32_get_flags
+ ia32_get_flags,
+ ia32_set_stack_bias
};
ia32_irn_ops_t ia32_irn_ops = {
* |___/
**************************************************/
-static void check_for_alloca(ir_node *irn, void *env) {
- int *has_alloca = env;
-
- if (get_irn_op(irn) == op_Alloc) {
- if (get_Alloc_where(irn) == stack_alloc) {
- *has_alloca = 1;
- }
- }
-}
-
/**
* Transforms the standard firm graph into
* an ia32 firm graph
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- if (! is_pseudo_ir_graph(cg->irg)) {
- /* If there is a alloca in the irg, we use %ebp for stack addressing */
- /* instead of %esp, as alloca destroys %esp. */
-
- cg->has_alloca = 0;
-
- /* check for alloca node */
- irg_walk_blkwise_graph(cg->irg, check_for_alloca, NULL, &(cg->has_alloca));
-
- if (cg->has_alloca) {
- ia32_general_purpose_regs[REG_EBP].type = arch_register_type_ignore;
- }
-
- irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
- }
+ irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
+ dump_ir_block_graph_sched(cg->irg, "-transformed");
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
+ dump_ir_block_graph_sched(cg->irg, "-am");
}
* Stack reservation and StackParam lowering.
*/
static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
+#if 0
firm_dbg_module_t *mod = cg->mod;
ir_node *frame = get_irg_frame(irg);
ir_node *end_block = get_irg_end_block(irg);
/* Determine stack register */
if (cg->has_alloca) {
- stack_reg = &ia32_general_purpose_regs[REG_EBP];
+ stack_reg = &ia32_gp_regs[REG_EBP];
}
else {
- stack_reg = &ia32_general_purpose_regs[REG_ESP];
+ stack_reg = &ia32_gp_regs[REG_ESP];
}
/* If frame is used, then we need to reserve some stackspace. */
/* get the old Return arguments */
n_arg = get_Return_n_ress(returns[i]);
in = get_Return_res_arr(returns[i]);
- new_in = xmalloc((n_arg + 2) * sizeof(new_in[0]));
-
- if (!new_in) {
- printf("\nMUAAAAHAHAHAHAHAHAHAH\n");
- exit(1);
- }
+ new_in = alloca((n_arg + 2) * sizeof(new_in[0]));
/* copy the old to the new in's */
memcpy(new_in, in, n_arg * sizeof(in[0]));
new_in[n_arg++] = get_Return_mem(returns[i]);
/* create the new return node */
- new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
- sched_point = sched_prev(returns[i]);
- sched_remove(returns[i]);
+ new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
+
+ /* In case the return node is the only node in the block, */
+ /* it is not scheduled, so we need this work-around. */
+ if (! sched_is_scheduled(returns[i])) {
+ sched_point = return_block;
+ }
+ else {
+ sched_point = sched_prev(returns[i]);
+ sched_remove(returns[i]);
+ }
/* exchange the old return with the new one */
exchange(returns[i], new_ret);
/* remove the old one from schedule and add the new nodes properly */
sched_add_after(sched_point, new_ret);
- sched_add_before(new_ret, stack_free);
+ sched_add_after(sched_point, stack_free);
}
}
+#endif
}
*/
static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
ia32_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
dbg_info *dbg = get_irn_dbg_info(spill);
ir_node *block = get_nodes_block(spill);
- ir_node *ptr = get_irg_frame(cg->irg);
+ ir_node *ptr = get_irg_frame(irg);
ir_node *val = be_get_Spill_context(spill);
- ir_node *mem = new_rd_NoMem(cg->irg);
+ ir_node *mem = new_rd_NoMem(irg);
ir_mode *mode = get_irn_mode(spill);
- ir_node *res;
entity *ent = be_get_spill_entity(spill);
unsigned offs = get_entity_offset_bytes(ent);
+ ir_node *noreg, *res;
+ char buf[64];
DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
- res = new_rd_ia32_Store(dbg, cg->irg, block, ptr, val, mem, mode);
- set_ia32_am_offs(res, new_tarval_from_long(offs, mode_Iu));
+ if (mode_is_float(mode)) {
+ noreg = ia32_new_NoReg_fp(cg);
+ res = new_rd_ia32_fStore(dbg, irg, block, ptr, noreg, val, mem, mode);
+ }
+ else {
+ noreg = ia32_new_NoReg_gp(cg);
+ res = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, mem, mode);
+ }
+
+ snprintf(buf, sizeof(buf), "%d", offs);
+ add_ia32_am_offs(res, buf);
return res;
}
*/
static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
ia32_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
dbg_info *dbg = get_irn_dbg_info(reload);
ir_node *block = get_nodes_block(reload);
- ir_node *ptr = get_irg_frame(cg->irg);
+ ir_node *ptr = get_irg_frame(irg);
ir_mode *mode = get_irn_mode(reload);
ir_node *pred = get_irn_n(reload, 0);
- tarval *tv;
- ir_node *res;
+ char buf[64];
+ char *ofs;
+ ir_node *noreg, *res;
+ /* Get the offset to Load from. It can either be a Spill or a Store. */
if (be_is_Spill(pred)) {
entity *ent = be_get_spill_entity(pred);
unsigned offs = get_entity_offset_bytes(ent);
DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
- tv = new_tarval_from_long(offs, mode_Iu);
+
+ snprintf(buf, sizeof(buf), "%d", offs);
}
- else if (is_ia32_Store(pred)) {
- tv = get_ia32_am_offs(pred);
+ else if (is_ia32_Store(pred) || is_ia32_fStore(pred)) {
+ ofs = get_ia32_am_offs(pred);
+ strncpy(buf, ofs, sizeof(buf));
+ free(ofs);
}
else {
assert(0 && "unsupported Reload predecessor");
}
- res = new_rd_ia32_Load(dbg, cg->irg, block, ptr, pred, mode);
- set_ia32_am_offs(res, tv);
-
- return res;
-}
-
-/**
- * Return the stack register for this irg.
- */
-static const arch_register_t *ia32_get_stack_register(void *self) {
- ia32_code_gen_t *cg = self;
-
- if (cg->has_alloca) {
- return &ia32_general_purpose_regs[REG_EBP];
+ /* Create the Load */
+ if (mode_is_float(mode)) {
+ noreg = ia32_new_NoReg_fp(cg);
+ res = new_rd_ia32_fLoad(dbg, irg, block, ptr, noreg, pred, mode_T);
}
+ else {
+ noreg = ia32_new_NoReg_gp(cg);
+ res = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, pred, mode_T);
+ }
+
+ /* Set offset */
+ add_ia32_am_offs(res, buf);
- return &ia32_general_purpose_regs[REG_ESP];
+ /* Return the result Proj */
+ return new_rd_Proj(dbg, irg, block, res, mode, 0);
}
/**
}
ia32_finish_irg(irg, cg);
- dump_ir_block_graph_sched(irg, "-finished");
+ //dump_ir_block_graph_sched(irg, "-finished");
ia32_gen_routine(out, irg, cg);
cur_reg_set = NULL;
+ pmap_destroy(cg->tv_ent);
+ pmap_destroy(cg->types);
+
/* de-allocate code generator */
del_set(cg->reg_set);
free(self);
ia32_before_ra, /* before register allocation hook */
ia32_lower_spill,
ia32_lower_reload,
- ia32_get_stack_register,
ia32_codegen /* emit && done */
};
*/
static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
- ia32_code_gen_t *cg = xmalloc(sizeof(*cg));
-
- cg->impl = &ia32_code_gen_if;
- cg->irg = irg;
- cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.ia32.cg");
- cg->out = F;
- cg->arch_env = arch_env;
+ ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
+
+ cg->impl = &ia32_code_gen_if;
+ cg->irg = irg;
+ cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
+ cg->mod = firm_dbg_register("firm.be.ia32.cg");
+ cg->out = F;
+ cg->arch_env = arch_env;
+ cg->types = pmap_create();
+ cg->tv_ent = pmap_create();
+ cg->noreg_gp = NULL;
+ cg->noreg_fp = NULL;
isa->num_codegens++;
*
*****************************************************************/
+static ia32_isa_t ia32_isa_template = {
+ &ia32_isa_if,
+ &ia32_gp_regs[REG_ESP],
+ &ia32_gp_regs[REG_EBP],
+ -1,
+ 0,
+ NULL
+};
+
/**
- * Initializes the backend ISA and opens the output file.
+ * Initializes the backend ISA.
*/
static void *ia32_init(void) {
static int inited = 0;
- ia32_isa_t *isa = xmalloc(sizeof(*isa));
-
- isa->impl = &ia32_isa_if;
+ ia32_isa_t *isa;
if(inited)
return NULL;
- inited = 1;
+ isa = xcalloc(1, sizeof(*isa));
+ memcpy(isa, &ia32_isa_template, sizeof(*isa));
- isa->num_codegens = 0;
isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
ia32_register_init(isa);
ia32_create_opcodes();
+ inited = 1;
+
return isa;
}
return &ia32_reg_classes[i];
}
+/**
+ * Get the register class which shall be used to store a value of a given mode.
+ * @param self The this pointer.
+ * @param mode The mode in question.
+ * @return A register class which can hold values of the given mode.
+ */
+const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
+ if (mode_is_float(mode))
+ return &ia32_reg_classes[CLASS_ia32_fp];
+ else
+ return &ia32_reg_classes[CLASS_ia32_gp];
+}
+
+/**
+ * Get the ABI restrictions for procedure calls.
+ * @param self The this pointer.
+ * @param method_type The type of the method (procedure) in question.
+ * @param abi The abi object to be modified
+ */
+void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+ ir_type *tp;
+ ir_mode *mode;
+ unsigned cc = get_method_calling_convention(method_type);
+ int n = get_method_n_params(method_type);
+ int biggest_n = -1;
+ int stack_idx = 0;
+ int i, ignore;
+ ir_mode **modes;
+ const arch_register_t *reg;
+
+ /* set stack parameter passing style */
+ be_abi_call_set_flags(abi, BE_ABI_FRAME_POINTER_DEDICATED, 4);
+
+ /* collect the mode for each type */
+ modes = alloca(n * sizeof(modes[0]));
+
+ for (i = 0; i < n; i++) {
+ tp = get_method_param_type(method_type, i);
+ modes[i] = get_type_mode(tp);
+ }
+
+ /* set register parameters */
+ if (cc & cc_reg_param) {
+ /* determine the number of parameters passed via registers */
+ biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
+
+ /* loop over all parameters and set the register requirements */
+ for (i = 0; i <= biggest_n; i++) {
+ reg = ia32_get_RegParam_reg(n, modes, i, cc);
+ assert(reg && "kaputt");
+ be_abi_call_param_reg(abi, i, reg);
+ }
+
+ stack_idx = i;
+ }
+
+
+ /* set stack parameters */
+ for (i = stack_idx; i < n; i++) {
+ be_abi_call_param_stack(abi, i);
+ }
+
+
+ /* set return registers */
+ n = get_method_n_ress(method_type);
+
+ assert(n <= 2 && "more than two results not supported");
+
+ /* In case of 64bit returns, we will have two 32bit values */
+ if (n == 2) {
+ tp = get_method_res_type(method_type, 0);
+ mode = get_type_mode(tp);
+
+ assert(!mode_is_float(mode) && "two FP results not supported");
+
+ tp = get_method_res_type(method_type, 1);
+ mode = get_type_mode(tp);
+
+ assert(!mode_is_float(mode) && "two FP results not supported");
+
+ be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
+ be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
+ }
+ else if (n == 1) {
+ tp = get_method_res_type(method_type, 0);
+ mode = get_type_mode(tp);
+
+ if (mode_is_float(mode)) {
+ be_abi_call_res_reg(abi, 1, &ia32_fp_regs[REG_XMM0]);
+ }
+ else {
+ be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EAX]);
+ }
+ }
+}
+
+
static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
return &ia32_irn_ops;
}
assert(pn == 0 && "only one floating point result supported");
/* Get the proj number for the floating point result */
- pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_XMM0], isa->reg_projnum_map);
+ pn = ia32_get_reg_projnum(&ia32_fp_regs[REG_XMM0], isa->reg_projnum_map);
}
else {
/* In case of 64bit return value, the result is */
/* in EDX:EAX and we have two result projs. */
switch (pn) {
case 0:
- pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_EAX], isa->reg_projnum_map);
+ pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EAX], isa->reg_projnum_map);
break;
case 1:
- pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_EDX], isa->reg_projnum_map);
+ pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EDX], isa->reg_projnum_map);
break;
default:
assert(0 && "only two int results supported");
}
else {
/* Set mode to floating point if required */
- if (!strcmp(ia32_reg_classes[CLASS_ia32_floating_point].name,
+ if (!strcmp(ia32_reg_classes[CLASS_ia32_fp].name,
ia32_projnum_reg_req_map[pn]->req.cls->name)) {
set_irn_mode(proj, mode_F);
}
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
- memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
+ memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
ia32_done,
ia32_get_n_reg_class,
ia32_get_reg_class,
+ ia32_get_reg_class_for_mode,
+ ia32_get_call_abi,
ia32_get_irn_handler,
ia32_get_code_generator_if,
ia32_get_list_sched_selector,
projects / libfirm / blobdiff