* @author Christian Wuerdig
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include "lc_opts.h"
#include "lc_opts_enum.h"
#include "../begnuas.h"
#include "../bestate.h"
#include "../beflags.h"
+#include "../betranshlp.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
#include "gen_ia32_machine.h"
+#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_emitter.h"
#include "ia32_map_regs.h"
#ifdef FIRM_GRGEN_BE
#include "ia32_pbqp_transform.h"
+
+transformer_t be_transformer = TRANSFORMER_DEFAULT;
#endif
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
-static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
+static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
create_const_node_func func,
const arch_register_t* reg)
{
block = get_irg_start_block(cg->irg);
res = func(NULL, cg->irg, block);
- arch_set_irn_register(cg->arch_env, res, reg);
+ arch_set_irn_register(res, reg);
*place = res;
add_irn_dep(get_irg_end(cg->irg), res);
/**
* Returns the admissible noreg register node for input register pos of node irn.
*/
-ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
- const arch_register_req_t *req;
+static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
+{
+ const arch_register_req_t *req = arch_get_register_req(irn, pos);
- req = arch_get_register_req(cg->arch_env, irn, pos);
assert(req != NULL && "Missing register requirements");
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
return ia32_new_NoReg_gp(cg);
static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
{
int pos = 0;
- const arch_register_t *reg = NULL;
if (is_Proj(irn)) {
-
if (get_irn_mode(irn) == mode_X) {
return NULL;
}
}
if (is_ia32_irn(irn)) {
- const arch_register_t **slots;
- slots = get_ia32_slots(irn);
+ const arch_register_t **slots = get_ia32_slots(irn);
assert(pos < get_ia32_n_res(irn));
- reg = slots[pos];
+ return slots[pos];
} else {
- reg = ia32_get_firm_reg(irn, cur_reg_set);
+ return ia32_get_firm_reg(irn, cur_reg_set);
}
-
- return reg;
}
static arch_irn_class_t ia32_classify(const ir_node *irn) {
- arch_irn_class_t classification = arch_irn_class_normal;
+ arch_irn_class_t classification = 0;
irn = skip_Proj_const(irn);
classification |= arch_irn_class_branch;
if (! is_ia32_irn(irn))
- return classification & ~arch_irn_class_normal;
+ return classification;
- if (is_ia32_Ld(irn))
- classification |= arch_irn_class_load;
+ if (is_ia32_is_reload(irn))
+ classification |= arch_irn_class_reload;
- if (is_ia32_St(irn))
- classification |= arch_irn_class_store;
+ if (is_ia32_is_spill(irn))
+ classification |= arch_irn_class_spill;
- if (is_ia32_need_stackent(irn))
- classification |= arch_irn_class_reload;
+ if (is_ia32_is_remat(irn))
+ classification |= arch_irn_class_remat;
return classification;
}
static int ia32_get_sp_bias(const ir_node *node)
{
+ if (is_ia32_Call(node))
+ return -(int)get_ia32_call_attr_const(node)->pop;
+
if (is_ia32_Push(node))
return 4;
/**
* Generate the routine prologue.
*
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
*
- * @return The register which shall be used as a stack frame base.
+ * @return The register which shall be used as a stack frame base.
*
* All nodes which define registers in @p reg_map must keep @p reg_map current.
*/
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
ia32_abi_env_t *env = self;
ia32_code_gen_t *cg = ia32_current_cg;
*mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
/* the push must have SP out register */
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
+ arch_set_irn_register(curr_sp, arch_env->sp);
set_ia32_flags(push, arch_irn_flags_ignore);
+ /* this modifies the stack bias, because we pushed 32bit */
+ *stack_bias -= 4;
+
/* move esp to ebp */
curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
- arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
+ arch_set_irn_register(curr_bp, arch_env->bp);
be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* beware: the copy must be done before any other sp use */
curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
+ arch_set_irn_register(curr_sp, arch_env->sp);
be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
if (env->flags.try_omit_fp) {
/* simply remove the stack frame here */
curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
- add_irn_dep(curr_sp, *mem);
} else {
ir_mode *mode_bp = arch_env->bp->reg_class->mode;
ir_node *leave;
/* leave */
- leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
+ leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
set_ia32_flags(leave, arch_irn_flags_ignore);
curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
/* the old SP is not needed anymore (kill the proj) */
assert(is_Proj(curr_sp));
- be_kill_node(curr_sp);
+ kill_node(curr_sp);
/* copy ebp to esp */
curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
+ arch_set_irn_register(curr_sp, arch_env->sp);
be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* pop ebp */
*mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
}
- arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
- arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
+ arch_set_irn_register(curr_sp, arch_env->sp);
+ arch_set_irn_register(curr_bp, arch_env->bp);
}
be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
*/
static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
{
- ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
env->aenv = aenv;
(we assume they are in cache), other memory operations cost 20
cycles.
*/
- if(is_ia32_use_frame(irn) ||
- (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
- is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
+ if (is_ia32_use_frame(irn) || (
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+ )) {
cost += 5;
} else {
cost += 20;
*/
static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
{
- if(mode_is_float(mode)) {
- return mode == spillmode;
- } else {
- return 1;
- }
+ return !mode_is_float(mode) || mode == spillmode;
}
/**
* Check if irn can load its operand at position i from memory (source addressmode).
- * @param self Pointer to irn ops itself
* @param irn The irn to be checked
* @param i The operands position
* @return Non-Zero if operand can be loaded
*/
-static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
- ir_node *op = get_irn_n(irn, i);
- const ir_mode *mode = get_irn_mode(op);
+static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
+{
+ ir_node *op = get_irn_n(irn, i);
+ const ir_mode *mode = get_irn_mode(op);
const ir_mode *spillmode = get_spill_mode(op);
- if (
- (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
- ! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
- get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
- ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
- ! ia32_is_spillmode_compatible(mode, spillmode) ||
- is_ia32_use_frame(irn)) /* must not already use frame */
+ if (!is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ !ia32_is_spillmode_compatible(mode, spillmode) ||
+ is_ia32_use_frame(irn)) /* must not already use frame */
return 0;
- if (i == n_ia32_binary_left) {
- const arch_register_req_t *req;
- if(!is_ia32_commutative(irn))
- return 0;
- /* we can't swap left/right for limited registers
- * (As this (currently) breaks constraint handling copies)
- */
- req = get_ia32_in_req(irn, n_ia32_binary_left);
- if (req->type & arch_register_req_type_limited) {
+ switch (get_ia32_am_support(irn)) {
+ case ia32_am_none:
return 0;
- }
+
+ case ia32_am_unary:
+ if (i != n_ia32_unary_op)
+ return 0;
+ break;
+
+ case ia32_am_binary:
+ switch (i) {
+ case n_ia32_binary_left: {
+ const arch_register_req_t *req;
+ if (!is_ia32_commutative(irn))
+ return 0;
+
+ /* we can't swap left/right for limited registers
+ * (As this (currently) breaks constraint handling copies)
+ */
+ req = get_ia32_in_req(irn, n_ia32_binary_left);
+ if (req->type & arch_register_req_type_limited)
+ return 0;
+ break;
+ }
+
+ case n_ia32_binary_right:
+ break;
+
+ default:
+ return 0;
+ }
+ break;
+
+ default:
+ panic("Unknown AM type");
}
+ /* HACK: must not already use "real" memory.
+ * This can happen for Call and Div */
+ if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
+ return 0;
+
return 1;
}
static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
unsigned int i)
{
- ia32_code_gen_t *cg = ia32_current_cg;
+ ir_mode *load_mode;
+ ir_mode *dest_op_mode;
assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
- if (i == n_ia32_binary_left) {
- ia32_swap_left_right(irn);
- }
-
set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
+
+ load_mode = get_irn_mode(get_irn_n(irn, i));
+ dest_op_mode = get_ia32_ls_mode(irn);
+ if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
+ set_ia32_ls_mode(irn, load_mode);
+ }
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
- set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
- set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
- set_irn_n(irn, n_ia32_mem, spill);
-
- /* immediates are only allowed on the right side */
- if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
+ if (i == n_ia32_binary_left &&
+ get_ia32_am_support(irn) == ia32_am_binary &&
+ /* immediates are only allowed on the right side */
+ !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
ia32_swap_left_right(irn);
+ i = n_ia32_binary_right;
}
+
+ assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
+
+ set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, n_ia32_mem, spill);
+ set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
+ set_ia32_is_reload(irn);
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
static void ia32_before_abi(void *self) {
lower_mode_b_config_t lower_mode_b_config = {
mode_Iu, /* lowered mode */
- mode_Bu, /* prefered mode for set */
+ mode_Bu, /* preferred mode for set */
0, /* don't lower direct compares */
};
ia32_code_gen_t *cg = self;
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- /* do local optimisations */
+ /* do local optimizations */
optimize_graph_df(cg->irg);
/* TODO: we often have dead code reachable through out-edges here. So for
if (cg->dump)
be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
-#ifdef FIRM_GRGEN_BE
- // disable CSE, because of two-step node-construction
- set_opt_cse(0);
-
- /* transform nodes into assembler instructions by PBQP magic */
- ia32_transform_graph_by_pbqp(cg);
-
- if (cg->dump)
- be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
- set_opt_cse(1);
-#else
+ switch (be_transformer) {
+ case TRANSFORMER_DEFAULT:
+ /* transform remaining nodes into assembler instructions */
+ ia32_transform_graph(cg);
+ break;
- /* transform remaining nodes into assembler instructions */
- ia32_transform_graph(cg);
+#ifdef FIRM_GRGEN_BE
+ case TRANSFORMER_PBQP:
+ case TRANSFORMER_RAND:
+ /* transform nodes into assembler instructions by PBQP magic */
+ ia32_transform_graph_by_pbqp(cg);
+ break;
#endif
- /* do local optimisations (mainly CSE) */
+ default:
+ panic("invalid transformer");
+ }
+
+ /* do local optimizations (mainly CSE) */
optimize_graph_df(cg->irg);
if (cg->dump)
/* optimize address mode */
ia32_optimize_graph(cg);
- if (cg->dump)
- be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
-
/* do code placement, to optimize the position of constants */
place_code(cg->irg);
be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
}
-/**
- * Dummy functions for hooks we don't need but which must be filled.
- */
-static void ia32_before_sched(void *self) {
- (void) self;
-}
-
-static void turn_back_am(ir_node *node)
+ir_node *turn_back_am(ir_node *node)
{
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *base = get_irn_n(node, n_ia32_base);
ir_node *index = get_irn_n(node, n_ia32_index);
ir_node *mem = get_irn_n(node, n_ia32_mem);
- ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
- ir_node *load;
- ir_node *load_res;
- ir_node *mem_proj;
- const ir_edge_t *edge;
+ ir_node *noreg;
- load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
- load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+ ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+ ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
+ if (is_ia32_is_reload(node))
+ set_ia32_is_reload(load);
set_irn_n(node, n_ia32_mem, new_NoMem());
- switch (get_ia32_am_arity(node)) {
+ switch (get_ia32_am_support(node)) {
case ia32_am_unary:
set_irn_n(node, n_ia32_unary_op, load_res);
break;
case ia32_am_binary:
- if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
- assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
- is_ia32_Test(node) || is_ia32_Test8Bit(node));
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
set_irn_n(node, n_ia32_binary_left, load_res);
} else {
set_irn_n(node, n_ia32_binary_right, load_res);
}
break;
- case ia32_am_ternary:
- set_irn_n(node, n_ia32_binary_right, load_res);
- break;
-
- default: break;
+ default:
+ panic("Unknown AM type");
}
- set_irn_n(node, n_ia32_base, noreg);
+ noreg = ia32_new_NoReg_gp(ia32_current_cg);
+ set_irn_n(node, n_ia32_base, noreg);
set_irn_n(node, n_ia32_index, noreg);
set_ia32_am_offs_int(node, 0);
set_ia32_am_sc(node, NULL);
/* rewire mem-proj */
if (get_irn_mode(node) == mode_T) {
- mem_proj = NULL;
+ const ir_edge_t *edge;
foreach_out_edge(node, edge) {
ir_node *out = get_edge_src_irn(edge);
- if(get_irn_mode(out) == mode_M) {
- assert(mem_proj == NULL);
- mem_proj = out;
+ if (get_irn_mode(out) == mode_M) {
+ set_Proj_pred(out, load);
+ set_Proj_proj(out, pn_ia32_Load_M);
+ break;
}
}
-
- if(mem_proj != NULL) {
- set_Proj_pred(mem_proj, load);
- set_Proj_proj(mem_proj, pn_ia32_Load_M);
- }
}
set_ia32_op_type(node, ia32_Normal);
if (sched_is_scheduled(node))
sched_add_before(node, load);
+
+ return load_res;
}
static ir_node *flags_remat(ir_node *node, ir_node *after)
/**
* Called before the register allocator.
- * Calculate a block schedule here. We need it for the x87
- * simulator and the emitter.
*/
static void ia32_before_ra(void *self) {
ia32_code_gen_t *cg = self;
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
+ set_ia32_is_reload(new_op);
DBG_OPT_RELOAD2LD(node, new_op);
}
/* copy the register from the old node to the new Load */
- reg = arch_get_irn_register(cg->arch_env, node);
- arch_set_irn_register(cg->arch_env, new_op, reg);
+ reg = arch_get_irn_register(node);
+ arch_set_irn_register(new_op, reg);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
+ set_ia32_is_spill(store);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
DBG_OPT_SPILL2ST(node, store);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
set_ia32_ls_mode(push, mode_Is);
+ set_ia32_is_spill(push);
sched_add_before(schedpoint, push);
return push;
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
set_ia32_ls_mode(pop, mode_Is);
+ set_ia32_is_reload(pop);
sched_add_before(schedpoint, pop);
return pop;
}
-static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
+static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
+{
ir_graph *irg = get_irn_irg(node);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *sp;
sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
- arch_set_irn_register(cg->arch_env, sp, spreg);
+ arch_set_irn_register(sp, spreg);
return sp;
}
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
push = create_push(cg, node, node, sp, mem, inent);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
+ sp = create_spproj(node, push, pn_ia32_Push_stack);
if(entsize == 8) {
/* add another push after the first one */
push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
+ sp = create_spproj(node, push, pn_ia32_Push_stack);
}
set_irn_n(node, i, new_Bad());
assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
pop = create_pop(cg, node, node, sp, outent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
+ sp = create_spproj(node, pop, pn_ia32_Pop_stack);
if(entsize == 8) {
add_ia32_am_offs_int(pop, 4);
/* add another pop after the first one */
pop = create_pop(cg, node, node, sp, outent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
+ sp = create_spproj(node, pop, pn_ia32_Pop_stack);
}
pops[i] = pop;
*/
static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = data;
+ const ir_mode *mode;
+ int align;
if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
- const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
- int align = get_mode_size_bytes(mode);
- be_node_needs_frame_entity(env, node, mode, align);
- } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
- && is_ia32_use_frame(node)) {
- if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- const ia32_attr_t *attr = get_ia32_attr_const(node);
- int align = get_mode_size_bytes(mode);
-
- if(attr->data.need_64bit_stackent) {
- mode = mode_Ls;
+ mode = get_spill_mode_mode(get_irn_mode(node));
+ align = get_mode_size_bytes(mode);
+ } else if (is_ia32_irn(node) &&
+ get_ia32_frame_ent(node) == NULL &&
+ is_ia32_use_frame(node)) {
+ if (is_ia32_need_stackent(node))
+ goto need_stackent;
+
+ switch (get_ia32_irn_opcode(node)) {
+need_stackent:
+ case iro_ia32_Load: {
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+
+ if (attr->data.need_32bit_stackent) {
+ mode = mode_Is;
+ } else if (attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ } else {
+ mode = get_ia32_ls_mode(node);
+ if (is_ia32_is_reload(node))
+ mode = get_spill_mode_mode(mode);
+ }
+ align = get_mode_size_bytes(mode);
+ break;
}
- if(attr->data.need_32bit_stackent) {
- mode = mode_Is;
+
+ case iro_ia32_vfild:
+ case iro_ia32_vfld:
+ case iro_ia32_xLoad: {
+ mode = get_ia32_ls_mode(node);
+ align = 4;
+ break;
}
- be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
- || is_ia32_vfld(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = 4;
- be_node_needs_frame_entity(env, node, mode, align);
- } else if(is_ia32_FldCW(node)) {
- /* although 2 byte would be enough 4 byte performs best */
- const ir_mode *mode = mode_Iu;
- int align = 4;
- be_node_needs_frame_entity(env, node, mode, align);
- } else {
+
+ case iro_ia32_FldCW: {
+ /* although 2 byte would be enough 4 byte performs best */
+ mode = mode_Iu;
+ align = 4;
+ break;
+ }
+
+ default:
#ifndef NDEBUG
- assert(is_ia32_St(node) ||
- is_ia32_xStoreSimple(node) ||
- is_ia32_vfst(node) ||
- is_ia32_vfist(node) ||
- is_ia32_vfisttp(node) ||
- is_ia32_FnstCW(node));
+ panic("unexpected frame user while collection frame entity nodes");
+
+ case iro_ia32_FnstCW:
+ case iro_ia32_Store8Bit:
+ case iro_ia32_Store:
+ case iro_ia32_fst:
+ case iro_ia32_fstp:
+ case iro_ia32_vfist:
+ case iro_ia32_vfisttp:
+ case iro_ia32_vfst:
+ case iro_ia32_xStore:
+ case iro_ia32_xStoreSimple:
#endif
+ return;
}
+ } else {
+ return;
}
+ be_node_needs_frame_entity(env, node, mode, align);
}
/**
/* we might have to rewrite x87 virtual registers */
if (cg->do_x87_sim) {
- x87_simulate_graph(cg->arch_env, cg->birg);
+ x87_simulate_graph(cg->birg);
}
/* do peephole optimisations */
get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
cg->get_eip = get_eip;
- add_irn_dep(get_eip, get_irg_frame(cg->irg));
-
+ be_dep_on_frame(get_eip);
return get_eip;
}
ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
NULL, /* spill */
- ia32_before_sched, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
ia32_after_ra, /* after register allocation hook */
ia32_finish, /* called before codegen */
*/
static void *ia32_cg_init(be_irg_t *birg) {
ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
- ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
+ ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
cg->impl = &ia32_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
cg->isa = isa;
- cg->arch_env = birg->main_env->arch_env;
cg->birg = birg;
cg->blk_sched = NULL;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
&ia32_gp_regs[REG_ESP], /* stack pointer register */
&ia32_gp_regs[REG_EBP], /* base pointer register */
-1, /* stack direction */
- 4, /* power of two stack alignment, 2^4 == 16 */
+ 2, /* power of two stack alignment, 2^2 == 4 */
NULL, /* main environment */
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
#endif
};
+static void init_asm_constraints(void)
+{
+ be_init_default_asm_constraint_flags();
+
+ asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+ asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
+ asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
+
+ /* no support for autodecrement/autoincrement */
+ asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* no float consts */
+ asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* makes no sense on x86 */
+ asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* no support for sse consts yet */
+ asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* no support for x87 consts yet */
+ asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* no support for mmx registers yet */
+ asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ /* not available in 32bit mode */
+ asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+ asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+
+ /* no code yet to determine register class needed... */
+ asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+}
+
/**
* Initializes the backend ISA.
*/
static arch_env_t *ia32_init(FILE *file_handle) {
static int inited = 0;
ia32_isa_t *isa;
+ int i, n;
if (inited)
return NULL;
set_tarval_output_modes();
- isa = xmalloc(sizeof(*isa));
+ isa = XMALLOC(ia32_isa_t);
memcpy(isa, &ia32_isa_template, sizeof(*isa));
if(mode_fpcw == NULL) {
ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
#ifndef NDEBUG
- isa->name_obst = xmalloc(sizeof(*isa->name_obst));
+ isa->name_obst = XMALLOC(struct obstack);
obstack_init(isa->name_obst);
#endif /* NDEBUG */
intrinsic_env.isa = isa;
ia32_handle_intrinsics();
+ /* emit asm includes */
+ n = get_irp_n_asms();
+ for (i = 0; i < n; ++i) {
+ be_emit_cstring("#APP\n");
+ be_emit_ident(get_irp_asm(i));
+ be_emit_cstring("\n#NO_APP\n");
+ }
+
/* needed for the debug support */
be_gas_emit_switch_section(GAS_SECTION_TEXT);
be_emit_cstring(".Ltext0:\n");
ir_mode *mode;
unsigned cc;
int n, i, regnum;
+ int pop_amount = 0;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
+
(void) self;
/* set abi flags for calls */
call_flags.bits.store_args_sequential = 0;
/* call_flags.bits.try_omit_fp not changed: can handle both settings */
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
- call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
+ call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
/* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
cc = cc_cdecl_set;
} else {
cc = get_method_calling_convention(method_type);
- if (get_method_additional_properties(method_type) & mtp_property_private
- && (ia32_cg_config.optimize_cc)) {
+ if (get_method_additional_properties(method_type) & mtp_property_private &&
+ ia32_cg_config.optimize_cc) {
/* set the calling conventions to register parameter */
cc = (cc & ~cc_bits) | cc_reg_param;
}
/* we have to pop the shadow parameter ourself for compound calls */
if( (get_method_calling_convention(method_type) & cc_compound_ret)
&& !(cc & cc_reg_param)) {
- be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
+ pop_amount += get_mode_size_bytes(mode_P_data);
}
n = get_method_n_params(method_type);
/* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
* movl has a shorter opcode than mov[sz][bw]l */
ir_mode *load_mode = mode;
- if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
+
+ if (mode != NULL) {
+ unsigned size = get_mode_size_bytes(mode);
+
+ if (cc & cc_callee_clear_stk) {
+ pop_amount += (size + 3U) & ~3U;
+ }
+
+ if (size < 4) load_mode = mode_Iu;
+ }
+
be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
}
}
+ be_abi_call_set_pop(abi, pop_amount);
+
/* set return registers */
n = get_method_n_ress(method_type);
if (is_ia32_irn(irn)) {
ret = get_ia32_exec_units(irn);
- }
- else if (is_be_node(irn)) {
- if (be_is_Call(irn) || be_is_Return(irn)) {
+ } else if (is_be_node(irn)) {
+ if (be_is_Return(irn)) {
ret = _units_callret;
- }
- else if (be_is_Barrier(irn)) {
+ } else if (be_is_Barrier(irn)) {
ret = _units_dummy;
- }
- else {
- ret = _units_other;
+ } else {
+ ret = _units_other;
}
}
else {
return NULL;
}
+static void ia32_mark_remat(const void *self, ir_node *node) {
+ (void) self;
+ if (is_ia32_irn(node)) {
+ set_ia32_is_remat(node);
+ }
+}
+
/**
* Allows or disallows the creation of Psi nodes for the given Phi nodes.
* @return 1 if allowed, 0 otherwise
return 0;
}
+static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
+{
+ (void) self;
+ (void) c;
+
+ /* we already added all our simple flags to the flags modifier list in
+ * init, so this flag we don't know. */
+ return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int ia32_is_valid_clobber(const void *self, const char *clobber)
+{
+ (void) self;
+
+ return ia32_get_clobber_register(clobber) != NULL;
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
ia32_setup_cg_config();
+ /* doesn't really belong here, but this is the earliest place the backend
+ * is called... */
+ init_asm_constraints();
+
p.dep_param = &ad;
p.if_conv_info = &ifconv;
return &p;
(int*) &be_gas_flavour, gas_items
};
+#ifdef FIRM_GRGEN_BE
+static const lc_opt_enum_int_items_t transformer_items[] = {
+ { "default", TRANSFORMER_DEFAULT },
+ { "pbqp", TRANSFORMER_PBQP },
+ { "random", TRANSFORMER_RAND },
+ { NULL, 0 }
+};
+
+static lc_opt_enum_int_var_t transformer_var = {
+ (int*)&be_transformer, transformer_items
+};
+#endif
+
static const lc_opt_table_entry_t ia32_options[] = {
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
+#ifdef FIRM_GRGEN_BE
+ LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
+#endif
LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
&ia32_isa_template.arch_env.stack_alignment),
LC_OPT_LAST
ia32_get_allowed_execution_units,
ia32_get_machine,
ia32_get_irg_list,
+ ia32_mark_remat,
+ ia32_parse_asm_constraint,
+ ia32_is_valid_clobber
};
void ia32_init_emitter(void);
projects / libfirm / blobdiff