made code C89 compliant (changed unnamed union in attributes)

[libfirm] / ir / be / ia32 / bearch_ia32.c

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 3e0281e..e6d30c4 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -87,7 +87,7 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_re
        const ia32_register_req_t *irn_req;
        long                       node_pos = pos == -1 ? 0 : pos;
        ir_mode                   *mode     = is_Block(irn) ? NULL : get_irn_mode(irn);
-       firm_dbg_module_t         *mod      = firm_dbg_register(DEBUG_MODULE);
+       FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
 
        if (is_Block(irn) || mode == mode_M || mode == mode_X) {
                DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
@@ -421,7 +421,7 @@ static void ia32_prepare_graph(void *self) {
        ia32_code_gen_t *cg = self;
        firm_dbg_module_t *old_mod = cg->mod;
 
-       cg->mod = firm_dbg_register("firm.be.ia32.transform");
+       FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
        irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
        be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
 
@@ -496,6 +496,16 @@ static void ia32_finish_irg_walker(ir_node *irn, void *env) {
                }
        }
 
+       /* If we have a CondJmp with immediate, we need to    */
+       /* check if it's the right operand, otherwise we have */
+       /* to change it, as CMP doesn't support immediate as  */
+       /* left operands.                                     */
+       if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
+               long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
+               set_ia32_op_type(irn, ia32_AddrModeD);
+               set_ia32_pncode(irn, pnc);
+       }
+
        /* check if there is a sub which need to be transformed */
        ia32_transform_sub_to_neg_add(irn, cg);
 
@@ -553,7 +563,10 @@ static void transform_to_Load(ia32_transform_env_t *env) {
        }
 
        if (mode_is_float(mode)) {
-               new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+               if (USE_SSE2(env->cg))
+                       new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+               else
+                       new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
        }
        else {
                new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
@@ -579,8 +592,9 @@ static void transform_to_Load(ia32_transform_env_t *env) {
        reg = arch_get_irn_register(env->cg->arch_env, irn);
        arch_set_irn_register(env->cg->arch_env, new_op, reg);
 
-       exchange(irn, proj);
+       SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
 
+       exchange(irn, proj);
 }
 
 /**
@@ -602,7 +616,10 @@ static void transform_to_Store(ia32_transform_env_t *env) {
        }
 
        if (mode_is_float(mode)) {
-               new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+               if (USE_SSE2(env->cg))
+                       new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+               else
+                       new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
        }
        else if (get_mode_size_bits(mode) == 8) {
                new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
@@ -614,11 +631,11 @@ static void transform_to_Store(ia32_transform_env_t *env) {
        set_ia32_am_support(new_op, ia32_am_Dest);
        set_ia32_op_type(new_op, ia32_AddrModeD);
        set_ia32_am_flavour(new_op, ia32_B);
-       set_ia32_ls_mode(new_op, get_irn_mode(val));
+       set_ia32_ls_mode(new_op, mode);
        set_ia32_frame_ent(new_op, ent);
        set_ia32_use_frame(new_op);
 
-       proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+       proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
 
        if (sched_point) {
                sched_add_after(sched_point, new_op);
@@ -627,8 +644,9 @@ static void transform_to_Store(ia32_transform_env_t *env) {
                sched_remove(irn);
        }
 
-       exchange(irn, proj);
+       SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
 
+       exchange(irn, proj);
 }
 
 /**
@@ -654,7 +672,8 @@ static void ia32_after_ra_walker(ir_node *node, void *env) {
                transform_to_Load(&tenv);
        }
        else if (be_is_Spill(node)) {
-               tenv.mode = get_irn_mode(be_get_Spill_context(node));
+               /* we always spill the whole register  */
+               tenv.mode = mode_is_float(get_irn_mode(be_get_Spill_context(node))) ? mode_D : mode_Is;
                transform_to_Store(&tenv);
        }
 }
@@ -668,7 +687,7 @@ static void ia32_after_ra(void *self) {
        irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
 
        /* if we do x87 code generation, rewrite all the virtual instructions and registers */
-       if (USE_x87(cg)) {
+       if (cg->used_x87) {
                x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
                be_dump(cg->irg, "-x87", dump_ir_extblock_graph_sched);
        }
@@ -725,7 +744,6 @@ static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
        cg->impl      = &ia32_code_gen_if;
        cg->irg       = birg->irg;
        cg->reg_set   = new_set(ia32_cmp_irn_reg_assoc, 1024);
-       cg->mod       = firm_dbg_register("firm.be.ia32.cg");
        cg->out       = F;
        cg->arch_env  = birg->main_env->arch_env;
        cg->types     = pmap_create();
@@ -733,6 +751,9 @@ static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
        cg->birg      = birg;
        cg->blk_sched = NULL;
        cg->fp_kind   = isa->fp_kind;
+       cg->used_x87  = 0;
+
+       FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
 
        /* set optimizations */
        cg->opt.incdec    = 0;