+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
/**
- * This is the main ia32 firm backend driver.
- * @author Christian Wuerdig
- * $Id$
+ * @file
+ * @brief This is the main ia32 firm backend driver.
+ * @author Christian Wuerdig
+ * @version $Id$
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
#include "../be_t.h"
#include "../beirgmod.h"
#include "../be_dbgout.h"
arch_set_irn_register(cg->arch_env, res, reg);
*place = res;
-#if 0
- /* keep the node so it isn't accidently removed when unused ... */
- in[0] = res;
- keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
-#endif
add_irn_dep(get_irg_end(cg->irg), res);
/* add_irn_dep(get_irg_start(cg->irg), res); */
if (is_ia32_Ld(irn))
classification |= arch_irn_class_load;
- if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+ if (is_ia32_St(irn))
classification |= arch_irn_class_store;
if (is_ia32_need_stackent(irn))
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *push;
+ /* ALL nodes representing bp must be set to ignore. */
+ be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
+
/* push ebp */
push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
/* optimize address mode */
- ia32_optimize_addressmode(cg);
+ ia32_optimize_graph(cg);
if (cg->dump)
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
// create pushs
for(i = 0; i < arity; ++i) {
- ir_entity *ent = be_get_MemPerm_in_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(inent);
int entbits = get_type_size_bits(enttype);
+ int entbits2 = get_type_size_bits(get_entity_type(outent));
ir_node *mem = get_irn_n(node, i + 1);
ir_node *push;
- assert(get_entity_type(be_get_MemPerm_out_entity(node, i)) == enttype);
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- push = create_push(cg, node, node, sp, mem, ent);
+ push = create_push(cg, node, node, sp, mem, inent);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
if(entbits == 64) {
// add another push after the first one
- push = create_push(cg, node, node, sp, mem, ent);
+ push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
}
// create pops
for(i = arity - 1; i >= 0; --i) {
- ir_entity *ent = be_get_MemPerm_out_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(outent);
int entbits = get_type_size_bits(enttype);
+ int entbits2 = get_type_size_bits(get_entity_type(inent));
ir_node *pop;
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- pop = create_pop(cg, node, node, sp, ent);
+ pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
if(entbits == 64) {
add_ia32_am_offs_int(pop, 4);
// add another pop after the first one
- pop = create_pop(cg, node, node, sp, ent);
+ pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
}
be_node_needs_frame_entity(env, node, mode, align);
} else {
#ifndef NDEBUG
- if(!is_ia32_Store(node)
- && !is_ia32_xStore(node)
- && !is_ia32_xStoreSimple(node)
+ if(!is_ia32_St(node) && !is_ia32_xStoreSimple(node)
&& !is_ia32_vfist(node)
&& !is_ia32_GetST0(node)
&& !is_ia32_FnstCW(node)) {
&ia32_gp_regs[REG_EBP], /* base pointer register */
-1, /* stack direction */
NULL, /* main environment */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
},
{ NULL, }, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
+ NULL, /* 8bit register names high */
NULL, /* types */
NULL, /* tv_ents */
(0 |
IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
arch_pentium_4, /* instruction architecture */
arch_pentium_4, /* optimize for architecture */
- fp_sse2, /* use sse2 unit */
+ fp_x87, /* floating point mode */
NULL, /* current code generator */
#ifndef NDEBUG
NULL, /* name obstack */
}
be_emit_init_env(&isa->emit, file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->types = pmap_create();
- isa->tv_ent = pmap_create();
- isa->cpu = ia32_init_machine_description();
+ isa->regs_16bit = pmap_create();
+ isa->regs_8bit = pmap_create();
+ isa->regs_8bit_high = pmap_create();
+ isa->types = pmap_create();
+ isa->tv_ent = pmap_create();
+ isa->cpu = ia32_init_machine_description();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
+ ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
#ifndef NDEBUG
isa->name_obst = xmalloc(sizeof(*isa->name_obst));
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
+ pmap_destroy(isa->regs_8bit_high);
pmap_destroy(isa->tv_ent);
pmap_destroy(isa->types);
ir_mode *mode;
unsigned cc = get_method_calling_convention(method_type);
int n = get_method_n_params(method_type);
- int biggest_n = -1;
- int stack_idx = 0;
- int i, ignore_1, ignore_2;
- ir_mode **modes;
- const arch_register_t *reg;
+ int i;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
- /* set stack parameter passing style */
+ /* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
- /* collect the mode for each type */
- modes = alloca(n * sizeof(modes[0]));
-
for (i = 0; i < n; i++) {
- tp = get_method_param_type(method_type, i);
- modes[i] = get_type_mode(tp);
- }
+ const ir_mode *mode;
+ const arch_register_t *reg;
- /* set register parameters */
- if (cc & cc_reg_param) {
- /* determine the number of parameters passed via registers */
- biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
+ tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
+ reg = ia32_get_RegParam_reg(isa->cg, cc, i, mode);
- /* loop over all parameters and set the register requirements */
- for (i = 0; i <= biggest_n; i++) {
- reg = ia32_get_RegParam_reg(n, modes, i, cc);
- assert(reg && "kaputt");
+ if(reg != NULL) {
be_abi_call_param_reg(abi, i, reg);
+ } else {
+ be_abi_call_param_stack(abi, i, 4, 0, 0);
}
-
- stack_idx = i;
}
-
- /* set stack parameters */
- for (i = stack_idx; i < n; i++) {
- /* parameters on the stack are 32 bit aligned */
- be_abi_call_param_stack(abi, i, 4, 0, 0);
- }
-
-
/* set return registers */
n = get_method_n_ress(method_type);
}
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- if(!is_ia32_irn(irn))
+ if(!is_ia32_irn(irn)) {
return -1;
+ }
if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
|| is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
- || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn))
+ || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
+ || is_ia32_Immediate(irn))
return 0;
return 1;
32 /* Mulh allowed up to 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 1, /* support inline assembly */
+ 1, /* prefer fastcall calling convention */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
ia32_create_intrinsic_fkt,
&intrinsic_env, /* context for ia32_create_intrinsic_fkt */
NULL, /* will be set later */
projects / libfirm / blobdiff