#include "error.h"
#include "xmalloc.h"
#include "irtools.h"
+#include "iroptimize.h"
#include "../beabi.h"
#include "../beirg_t.h"
#include "../bemodule.h"
#include "../begnuas.h"
#include "../bestate.h"
+#include "../beflags.h"
#include "bearch_ia32_t.h"
#include "ia32_finish.h"
#include "ia32_util.h"
#include "ia32_fpu.h"
+#include "ia32_architecture.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
ir_mode *mode_fpcw = NULL;
ia32_code_gen_t *ia32_current_cg = NULL;
+/**
+ * The environment for the intrinsic mapping.
+ */
+static ia32_intrinsic_env_t intrinsic_env = {
+ NULL, /* the isa */
+ NULL, /* the irg, these entities belong to */
+ NULL, /* entity for first div operand (move into FPU) */
+ NULL, /* entity for second div operand (move into FPU) */
+ NULL, /* entity for converts ll -> d */
+ NULL, /* entity for converts d -> ll */
+ NULL, /* entity for __divdi3 library call */
+ NULL, /* entity for __moddi3 library call */
+ NULL, /* entity for __udivdi3 library call */
+ NULL, /* entity for __umoddi3 library call */
+ NULL, /* bias value for conversion from float to unsigned 64 */
+};
+
+
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
&ia32_xmm_regs[REG_XMM_NOREG]);
}
-/* Creates the unique per irg FP NoReg node. */
-ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
- return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
-}
-
ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
&ia32_gp_regs[REG_GP_UKNWN]);
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
return ia32_new_NoReg_gp(cg);
- return ia32_new_NoReg_fp(cg);
+ if (ia32_cg_config.use_sse2) {
+ return ia32_new_NoReg_xmm(cg);
+ } else {
+ return ia32_new_NoReg_vfp(cg);
+ }
}
/**************************************************
if (is_ia32_irn(irn)) {
const arch_register_t **slots;
slots = get_ia32_slots(irn);
+ assert(pos < get_ia32_n_res(irn));
reg = slots[pos];
} else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
- ia32_am_flavour_t am_flav;
-
if (is_ia32_Pop(irn)) {
int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
if (omit_fp) {
}
}
- am_flav = get_ia32_am_flavour(irn);
- am_flav |= ia32_O;
- set_ia32_am_flavour(irn, am_flav);
-
add_ia32_am_offs_int(irn, bias);
}
}
be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
} else {
const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
ia32_code_gen_t *cg = isa->cg;
- ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ ir_graph *irg = current_ir_graph;
- /* gcc always emits a leave at the end of a routine */
- if (1 || ARCH_AMD(isa->opt_arch)) {
+ if (ia32_cg_config.use_leave) {
ir_node *leave;
/* leave */
- leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
+ leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
set_ia32_flags(leave, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
- curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+ curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
} else {
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *pop;
+ /* the old SP is not needed anymore (kill the proj) */
+ assert(is_Proj(curr_sp));
+ be_kill_node(curr_sp);
+
/* copy ebp to esp */
- curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
+ curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
set_ia32_flags(pop, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
- curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+ curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
+ curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
- *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
+ *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
}
arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
*/
static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
{
- int cost;
+ int cost;
ia32_op_type_t op_tp;
- const ia32_irn_ops_t *ops = self;
+ (void) self;
if (is_Proj(irn))
return 0;
if (is_ia32_CopyB(irn)) {
cost = 250;
- if (ARCH_INTEL(ops->cg->arch))
- cost += 150;
}
else if (is_ia32_CopyB_i(irn)) {
- int size = get_tarval_long(get_ia32_Immop_tarval(irn));
+ int size = get_ia32_copyb_size(irn);
cost = 20 + (int)ceil((4/3) * size);
- if (ARCH_INTEL(ops->cg->arch))
- cost += 150;
}
/* in case of address mode operations add additional cycles */
else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
return NULL;
/* operand must always be a real operand (not base, index or mem) */
- if (i != 2 && i != 3)
+ if (i != n_ia32_binary_left && i != n_ia32_binary_right)
return NULL;
/* we don't invert address mode operations */
if (get_ia32_op_type(irn) != ia32_Normal)
return NULL;
+ /* TODO: adjust for new immediates... */
+ ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
+ irn);
+ return NULL;
+
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
+#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
+#endif
break;
case iro_ia32_Sub:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
- if (i == 2) {
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
+ if (i == n_ia32_binary_left) {
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Xor:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
const ir_mode *spillmode = get_spill_mode(op);
(void) self;
- if (! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_irn_arity(irn) != 5 || /* must be a binary operation */
- get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
- ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
- ! ia32_is_spillmode_compatible(mode, spillmode) ||
- (i != 2 && i != 3) || /* a "real" operand position must be requested */
- is_ia32_use_frame(irn)) /* must not already use frame */
+ if (! is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
+ ! ia32_is_spillmode_compatible(mode, spillmode) ||
+ (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
+ is_ia32_use_frame(irn)) /* must not already use frame */
return 0;
- if(i == 2) {
+ if (i == n_ia32_binary_left) {
const arch_register_req_t *req;
if(!is_ia32_commutative(irn))
return 0;
/* we can't swap left/right for limited registers
* (As this (currently) breaks constraint handling copies)
*/
- req = get_ia32_in_req(irn, 2);
+ req = get_ia32_in_req(irn, n_ia32_binary_left);
if(req->type & arch_register_req_type_limited) {
return 0;
}
assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
- if (i == 2) {
+ if (i == n_ia32_binary_left) {
ia32_swap_left_right(irn);
}
set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
- set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
- set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
- set_irn_n(irn, 4, spill);
+ set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
+ set_irn_n(irn, n_ia32_mem, spill);
/* immediates are only allowed on the right side */
- if(i == 2 && is_ia32_Immediate(get_irn_n(irn, 2))) {
+ if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
ia32_swap_left_right(irn);
}
}
ia32_perform_memory_operand,
};
-ia32_irn_ops_t ia32_irn_ops = {
+static ia32_irn_ops_t ia32_irn_ops = {
&ia32_irn_ops_if,
NULL
};
* |___/
**************************************************/
+static void ia32_before_abi(void *self) {
+ lower_mode_b_config_t lower_mode_b_config = {
+ mode_Iu, /* lowered mode */
+ mode_Bu, /* prefered mode for set */
+ 0, /* don't lower direct compares */
+ };
+ ia32_code_gen_t *cg = self;
+
+ ir_lower_mode_b(cg->irg, &lower_mode_b_config);
+ if(cg->dump)
+ be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+}
+
/**
* Transforms the standard firm graph into
* an ia32 firm graph
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- ir_lower_mode_b(cg->irg, mode_Iu, 0);
/* do local optimisations */
optimize_graph_df(cg->irg);
+
+ /* TODO: we often have dead code reachable through out-edges here. So for
+ * now we rebuild edges (as we need correct user count for code selection)
+ */
+#if 1
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+#endif
+
if(cg->dump)
- be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+ be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
/* transform nodes into assembler instructions */
ia32_transform_graph(cg);
(void) self;
}
+static void turn_back_am(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *mem = get_irn_n(node, n_ia32_mem);
+ ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
+ ir_node *load;
+ ir_node *load_res;
+ ir_node *mem_proj;
+ const ir_edge_t *edge;
+
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+ load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+
+ ia32_copy_am_attrs(load, node);
+ set_irn_n(node, n_ia32_mem, new_NoMem());
+
+ switch (get_ia32_am_arity(node)) {
+ case ia32_am_unary:
+ set_irn_n(node, n_ia32_unary_op, load_res);
+ break;
+
+ case ia32_am_binary:
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
+ assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
+ is_ia32_Test(node) || is_ia32_Test8Bit(node));
+ set_irn_n(node, n_ia32_binary_left, load_res);
+ } else {
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ }
+ break;
+
+ case ia32_am_ternary:
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ break;
+
+ default: break;
+ }
+ set_irn_n(node, n_ia32_base, noreg);
+ set_irn_n(node, n_ia32_index, noreg);
+ set_ia32_am_offs_int(node, 0);
+ set_ia32_am_sc(node, NULL);
+ set_ia32_am_scale(node, 0);
+ clear_ia32_am_sc_sign(node);
+
+ /* rewire mem-proj */
+ if(get_irn_mode(node) == mode_T) {
+ mem_proj = NULL;
+ foreach_out_edge(node, edge) {
+ ir_node *out = get_edge_src_irn(edge);
+ if(get_Proj_proj(out) == pn_ia32_mem) {
+ mem_proj = out;
+ break;
+ }
+ }
+
+ if(mem_proj != NULL) {
+ set_Proj_pred(mem_proj, load);
+ set_Proj_proj(mem_proj, pn_ia32_Load_M);
+ }
+ }
+
+ set_ia32_op_type(node, ia32_Normal);
+ if(sched_is_scheduled(node))
+ sched_add_before(node, load);
+}
+
+static ir_node *flags_remat(ir_node *node, ir_node *after)
+{
+ /* we should turn back source address mode when rematerializing nodes */
+ ia32_op_type_t type = get_ia32_op_type(node);
+ ir_node *block;
+ ir_node *copy;
+
+ if(is_Block(after)) {
+ block = after;
+ } else {
+ block = get_nodes_block(after);
+ }
+
+ switch (type) {
+ case ia32_AddrModeS: turn_back_am(node); break;
+
+ case ia32_AddrModeD:
+ /* TODO implement this later... */
+ panic("found DestAM with flag user %+F this should not happen", node);
+ break;
+
+ default: assert(type == ia32_Normal); break;
+ }
+
+ copy = exact_copy(node);
+ set_nodes_block(copy, block);
+ sched_add_after(after, copy);
+
+ return copy;
+}
+
/**
* Called before the register allocator.
* Calculate a block schedule here. We need it for the x87
* simulator and the emitter.
*/
static void ia32_before_ra(void *self) {
- ia32_code_gen_t *cg = self;
+ ia32_code_gen_t *cg = self;
/* setup fpu rounding modes */
ia32_setup_fpu_mode(cg);
+
+ /* fixup flags */
+ be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
+ &flags_remat);
+
+ ia32_add_missing_keeps(cg);
}
}
if (mode_is_float(spillmode)) {
- if (USE_SSE2(cg))
- new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
+ if (ia32_cg_config.use_sse2)
+ new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
}
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
}
if (mode_is_float(mode)) {
- if (USE_SSE2(cg))
- store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
+ if (ia32_cg_config.use_sse2)
+ store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
else
- store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem, mode);
+ store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
} else if (get_mode_size_bits(mode) == 128) {
// Spill 128 bit SSE registers
- store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
} else {
- store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
}
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
+ ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
- set_ia32_am_flavour(push, ia32_B);
set_ia32_ls_mode(push, mode_Is);
sched_add_before(schedpoint, push);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
+ ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
- set_ia32_am_flavour(pop, ia32_am_OB);
set_ia32_ls_mode(pop, mode_Is);
sched_add_before(schedpoint, pop);
arity = be_get_MemPerm_entity_arity(node);
pops = alloca(arity * sizeof(pops[0]));
- // create pushs
+ /* create Pushs */
for(i = 0; i < arity; ++i) {
ir_entity *inent = be_get_MemPerm_in_entity(node, i);
ir_entity *outent = be_get_MemPerm_out_entity(node, i);
ir_type *enttype = get_entity_type(inent);
- int entbits = get_type_size_bits(enttype);
- int entbits2 = get_type_size_bits(get_entity_type(outent));
+ unsigned entsize = get_type_size_bytes(enttype);
+ unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
ir_node *mem = get_irn_n(node, i + 1);
ir_node *push;
/* work around cases where entities have different sizes */
- if(entbits2 < entbits)
- entbits = entbits2;
- assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+ if(entsize2 < entsize)
+ entsize = entsize2;
+ assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
push = create_push(cg, node, node, sp, mem, inent);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
- if(entbits == 64) {
- // add another push after the first one
+ if(entsize == 8) {
+ /* add another push after the first one */
push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
set_irn_n(node, i, new_Bad());
}
- // create pops
+ /* create pops */
for(i = arity - 1; i >= 0; --i) {
ir_entity *inent = be_get_MemPerm_in_entity(node, i);
ir_entity *outent = be_get_MemPerm_out_entity(node, i);
ir_type *enttype = get_entity_type(outent);
- int entbits = get_type_size_bits(enttype);
- int entbits2 = get_type_size_bits(get_entity_type(inent));
+ unsigned entsize = get_type_size_bytes(enttype);
+ unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
ir_node *pop;
/* work around cases where entities have different sizes */
- if(entbits2 < entbits)
- entbits = entbits2;
- assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+ if(entsize2 < entsize)
+ entsize = entsize2;
+ assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
- if(entbits == 64) {
+ if(entsize == 8) {
add_ia32_am_offs_int(pop, 4);
- // add another pop after the first one
+ /* add another pop after the first one */
pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
}
}
in[0] = sp;
- keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+ keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
sched_add_before(node, keep);
- // exchange memprojs
+ /* exchange memprojs */
foreach_out_edge_safe(node, edge, next) {
ir_node *proj = get_edge_src_irn(edge);
int p = get_Proj_proj(proj);
set_Proj_proj(proj, pn_ia32_Pop_M);
}
- // remove memperm
+ /* remove memperm */
arity = get_irn_arity(node);
for(i = 0; i < arity; ++i) {
set_irn_n(node, i, new_Bad());
be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
|| is_ia32_vfld(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = 4;
+ const ir_mode *mode = get_ia32_ls_mode(node);
+ int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
} else if(is_ia32_FldCW(node)) {
- const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
- int align = 4;
+ /* although 2 byte would be enough 4 byte performs best */
+ const ir_mode *mode = mode_Iu;
+ int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
} else {
#ifndef NDEBUG
be_free_frame_entity_coalescer(fec_env);
irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
-
- ia32_finish_irg(irg, cg);
}
/**
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
+ ia32_finish_irg(irg, cg);
+
/* we might have to rewrite x87 virtual registers */
if (cg->do_x87_sim) {
x87_simulate_graph(cg->arch_env, cg->birg);
}
+ /* do peephole optimisations */
+ ia32_peephole_optimization(cg);
+
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
-
- /* do peephole optimisations */
- ia32_peephole_optimization(irg, cg);
}
/**
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
- NULL, /* before abi introduce hook */
+ ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
NULL, /* spill */
ia32_before_sched, /* before scheduling hook */
cg->isa = isa;
cg->birg = birg;
cg->blk_sched = NULL;
- cg->fp_kind = isa->fp_kind;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- /* copy optimizations from isa for easier access */
- cg->opt = isa->opt;
- cg->arch = isa->arch;
- cg->opt_arch = isa->opt_arch;
-
/* enter it */
isa->cg = cg;
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
},
- NULL_EMITTER, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* 8bit register names high */
NULL, /* types */
NULL, /* tv_ents */
- (0 |
- IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
- IA32_OPT_DOAM | /* optimize address mode default: on */
- IA32_OPT_LEA | /* optimize for LEAs default: on */
- IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
- IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
- IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
- arch_pentium_4, /* instruction architecture */
- arch_pentium_4, /* optimize for architecture */
- fp_x87, /* floating point mode */
NULL, /* current code generator */
+ NULL, /* abstract machine */
#ifndef NDEBUG
NULL, /* name obstack */
- 0 /* name obst size */
#endif
};
ia32_register_init();
ia32_create_opcodes();
- if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
- (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
- /* no SSE2 for these cpu's */
- isa->fp_kind = fp_x87;
-
- if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
- /* Pentium 4 don't like inc and dec instructions */
- isa->opt &= ~IA32_OPT_INCDEC;
- }
-
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
isa->regs_8bit_high = pmap_create();
obstack_init(isa->name_obst);
#endif /* NDEBUG */
+ /* enter the ISA object into the intrinsic environment */
+ intrinsic_env.isa = isa;
ia32_handle_intrinsics();
/* needed for the debug support */
- be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
- be_emit_cstring(&isa->emit, ".Ltext0:\n");
- be_emit_write_line(&isa->emit);
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
/* we mark referenced global entities, so we can only emit those which
* are actually referenced. (Note: you mustn't use the type visited flag
ia32_isa_t *isa = self;
/* emit now all global declarations */
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_isa.main_env, 1);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(self);
}
* - the virtual floating point registers
* - the SSE vector register set
*/
-static int ia32_get_n_reg_class(const void *self) {
+static unsigned ia32_get_n_reg_class(const void *self) {
(void) self;
return N_CLASSES;
}
/**
* Return the register class for index i.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
+static const arch_register_class_t *ia32_get_reg_class(const void *self,
+ unsigned i)
{
(void) self;
- assert(i >= 0 && i < N_CLASSES);
+ assert(i < N_CLASSES);
return &ia32_reg_classes[i];
}
* @param mode The mode in question.
* @return A register class which can hold values of the given mode.
*/
-const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
- const ia32_isa_t *isa = self;
+const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
+ const ir_mode *mode)
+{
+ (void) self;
+
if (mode_is_float(mode)) {
- return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
+ return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
}
else
return &ia32_reg_classes[CLASS_ia32_gp];
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
- const ia32_isa_t *isa = self;
+static void ia32_get_call_abi(const void *self, ir_type *method_type,
+ be_abi_call_t *abi)
+{
ir_type *tp;
ir_mode *mode;
unsigned cc;
int n, i, regnum;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
-
- unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
+ (void) self;
/* set abi flags for calls */
call_flags.bits.left_to_right = 0; /* always last arg first on stack */
- call_flags.bits.store_args_sequential = use_push;
+ call_flags.bits.store_args_sequential = 0;
/* call_flags.bits.try_omit_fp not changed: can handle both settings */
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
cc = cc_cdecl_set;
} else {
cc = get_method_calling_convention(method_type);
- if (get_method_additional_properties(method_type) & mtp_property_private) {
+ if (get_method_additional_properties(method_type) & mtp_property_private
+ && (ia32_cg_config.optimize_cc)) {
/* set the calling conventions to register parameter */
cc = (cc & ~cc_bits) | cc_reg_param;
}
}
+
+ /* we have to pop the shadow parameter ourself for compound calls */
+ if( (get_method_calling_convention(method_type) & cc_compound_ret)
+ && !(cc & cc_reg_param)) {
+ be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
+ }
+
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- const ir_mode *mode;
+ ir_mode *mode;
const arch_register_t *reg = NULL;
tp = get_method_param_type(method_type, i);
mode = get_type_mode(tp);
if (mode != NULL) {
- reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
+ reg = ia32_get_RegParam_reg(cc, regnum, mode);
}
if (reg != NULL) {
be_abi_call_param_reg(abi, i, reg);
++regnum;
} else {
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
+ * movl has a shorter opcode than mov[sz][bw]l */
+ ir_mode *load_mode = mode;
+ if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
+ be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
}
}
(void)i;
(void)j;
-#if 1
+ if(!ia32_cg_config.use_cmov) {
+ /* TODO: we could still handle abs(x)... */
+ return 0;
+ }
+
+ /* we can't handle psis with 64bit compares yet */
if(is_Proj(sel)) {
ir_node *pred = get_Proj_pred(sel);
if(is_Cmp(pred)) {
ir_node *left = get_Cmp_left(pred);
ir_mode *cmp_mode = get_irn_mode(left);
- if(mode_is_float(cmp_mode))
+ if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
return 0;
}
}
-#endif
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
return 1;
}
-static ia32_intrinsic_env_t intrinsic_env = {
- NULL, /**< the irg, these entities belong to */
- NULL, /**< entity for first div operand (move into FPU) */
- NULL, /**< entity for second div operand (move into FPU) */
- NULL, /**< entity for converts ll -> d */
- NULL, /**< entity for converts d -> ll */
- NULL, /**< entity for __divdi3 library call */
- NULL, /**< entity for __moddi3 library call */
- NULL, /**< entity for __udivdi3 library call */
- NULL, /**< entity for __umoddi3 library call */
-};
-
/**
* Returns the libFirm configuration parameter for this backend.
*/
ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
};
static const ir_settings_arch_dep_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 31, /* maximum shift amount */
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 31, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* allow Mulus */
NULL, /* will be set below */
};
+ ia32_setup_cg_config();
+
p.dep_param = &ad;
p.if_conv_info = &ifconv;
return &p;
}
-/* instruction set architectures. */
-static const lc_opt_enum_int_items_t arch_items[] = {
- { "386", arch_i386, },
- { "486", arch_i486, },
- { "pentium", arch_pentium, },
- { "586", arch_pentium, },
- { "pentiumpro", arch_pentium_pro, },
- { "686", arch_pentium_pro, },
- { "pentiummmx", arch_pentium_mmx, },
- { "pentium2", arch_pentium_2, },
- { "p2", arch_pentium_2, },
- { "pentium3", arch_pentium_3, },
- { "p3", arch_pentium_3, },
- { "pentium4", arch_pentium_4, },
- { "p4", arch_pentium_4, },
- { "pentiumm", arch_pentium_m, },
- { "pm", arch_pentium_m, },
- { "core", arch_core, },
- { "k6", arch_k6, },
- { "athlon", arch_athlon, },
- { "athlon64", arch_athlon_64, },
- { "opteron", arch_opteron, },
- { NULL, 0 }
-};
-
-static lc_opt_enum_int_var_t arch_var = {
- &ia32_isa_template.arch, arch_items
-};
-
-static lc_opt_enum_int_var_t opt_arch_var = {
- &ia32_isa_template.opt_arch, arch_items
-};
-
-static const lc_opt_enum_int_items_t fp_unit_items[] = {
- { "x87" , fp_x87 },
- { "sse2", fp_sse2 },
- { NULL, 0 }
-};
-
-static lc_opt_enum_int_var_t fp_unit_var = {
- &ia32_isa_template.fp_kind, fp_unit_items
-};
-
static const lc_opt_enum_int_items_t gas_items[] = {
{ "normal", GAS_FLAVOUR_NORMAL },
{ "mingw", GAS_FLAVOUR_MINGW },
};
static const lc_opt_table_entry_t ia32_options[] = {
- LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
- LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
- LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
- LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
- LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
- LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
- LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
- LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
- LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
+ LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
LC_OPT_LAST
};
void be_init_arch_ia32(void)
{
- lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+ lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
lc_opt_add_table(ia32_grp, ia32_options);
ia32_init_optimize();
ia32_init_transform();
ia32_init_x87();
+ ia32_init_architecture();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
projects / libfirm / blobdiff