#include "../be_dbgout.h"
#include "../beblocksched.h"
#include "../bemachine.h"
-#include "../beilpsched.h"
#include "../bespillslots.h"
#include "../bemodule.h"
#include "../begnuas.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-ir_mode *mode_fpcw = NULL;
+ir_mode *ia32_mode_fpcw = NULL;
/** The current omit-fp state */
static unsigned ia32_curr_fp_ommitted = 0;
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
- &ia32_gp_regs[REG_GP_NOREG]);
+ &ia32_registers[REG_GP_NOREG]);
}
ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
- &ia32_vfp_regs[REG_VFP_NOREG]);
+ &ia32_registers[REG_VFP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
- &ia32_xmm_regs[REG_XMM_NOREG]);
+ &ia32_registers[REG_XMM_NOREG]);
}
ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
- &ia32_fp_cw_regs[REG_FPCW]);
+ &ia32_registers[REG_FPCW]);
}
static arch_irn_class_t ia32_classify(const ir_node *irn)
{
- arch_irn_class_t classification = 0;
+ arch_irn_class_t classification = arch_irn_class_none;
assert(is_ia32_irn(irn));
*/
static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
ir_graph *irg = env->irg;
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
*/
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
*/
static ir_type *ia32_abi_get_between_type(void *self)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
ia32_build_between_type();
return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
cycles.
*/
if (is_ia32_use_frame(irn) || (
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
)) {
cost += 5;
} else {
mode = get_irn_mode(irn);
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
- nomem = new_NoMem();
+ nomem = new_r_NoMem(irg);
dbg = get_irn_dbg_info(irn);
/* initialize structure */
dump_ir_graph(irg, "place");
}
-ir_node *turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
{
dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
ir_node *base = get_irn_n(node, n_ia32_base);
ir_node *index = get_irn_n(node, n_ia32_index);
ia32_copy_am_attrs(load, node);
if (is_ia32_is_reload(node))
set_ia32_is_reload(load);
- set_irn_n(node, n_ia32_mem, new_NoMem());
+ set_irn_n(node, n_ia32_mem, new_r_NoMem(irg));
switch (get_ia32_am_support(node)) {
case ia32_am_unary:
type = get_ia32_op_type(node);
switch (type) {
case ia32_AddrModeS:
- turn_back_am(node);
+ ia32_turn_back_am(node);
break;
case ia32_AddrModeD:
const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
ir_mode *mode = get_spill_mode(spillval);
ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = new_r_NoMem(irg);
ir_node *ptr = get_irg_frame(irg);
ir_node *val = get_irn_n(node, be_pos_Spill_val);
ir_node *store;
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
+ ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_r_NoMem(irg), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
{
dbg_info *dbg = get_irn_dbg_info(node);
ir_mode *spmode = mode_Iu;
- const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
+ const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
sp = new_rd_Proj(dbg, pred, spmode, pos);
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_irn_irg(node);
- ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_gp_regs[REG_ESP]);
+ ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_registers[REG_ESP]);
int arity = be_get_MemPerm_entity_arity(node);
ir_node **pops = ALLOCAN(ir_node*, arity);
ir_node *in[1];
sp = create_spproj(node, push, pn_ia32_Push_stack);
}
- set_irn_n(node, i, new_Bad());
+ set_irn_n(node, i, new_r_Bad(irg));
}
/* create pops */
/* remove memperm */
arity = get_irn_arity(node);
for (i = 0; i < arity; ++i) {
- set_irn_n(node, i, new_Bad());
+ set_irn_n(node, i, new_r_Bad(irg));
}
sched_remove(node);
}
*/
static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = (be_fec_env_t*)data;
const ir_mode *mode;
int align;
/* we might have to rewrite x87 virtual registers */
if (irg_data->do_x87_sim) {
- x87_simulate_graph(irg);
+ ia32_x87_simulate_graph(irg);
}
/* do peephole optimisations */
}
}
-const arch_isa_if_t ia32_isa_if;
+extern const arch_isa_if_t ia32_isa_if;
/**
* The template that generates a new ISA object.
static ia32_isa_t ia32_isa_template = {
{
&ia32_isa_if, /* isa interface implementation */
- &ia32_gp_regs[REG_ESP], /* stack pointer register */
- &ia32_gp_regs[REG_EBP], /* base pointer register */
+ N_IA32_REGISTERS,
+ ia32_registers,
+ N_IA32_CLASSES,
+ ia32_reg_classes,
+ &ia32_registers[REG_ESP], /* stack pointer register */
+ &ia32_registers[REG_EBP], /* base pointer register */
&ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
-1, /* stack direction */
2, /* power of two stack alignment, 2^2 == 4 */
*/
static arch_env_t *ia32_init(FILE *file_handle)
{
- static int inited = 0;
- ia32_isa_t *isa;
+ ia32_isa_t *isa = XMALLOC(ia32_isa_t);
int i, n;
- if (inited)
- return NULL;
- inited = 1;
-
set_tarval_output_modes();
- isa = XMALLOC(ia32_isa_t);
memcpy(isa, &ia32_isa_template, sizeof(*isa));
- if (mode_fpcw == NULL) {
- mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ if (ia32_mode_fpcw == NULL) {
+ ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
}
ia32_register_init();
ia32_create_opcodes(&ia32_irn_ops);
be_emit_init(file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->regs_8bit_high = pmap_create();
isa->types = pmap_create();
isa->tv_ent = pmap_create();
isa->cpu = ia32_init_machine_description();
*/
static void ia32_done(void *self)
{
- ia32_isa_t *isa = self;
+ ia32_isa_t *isa = (ia32_isa_t*)self;
/* emit now all global declarations */
be_gas_emit_decls(isa->base.main_env);
- pmap_destroy(isa->regs_16bit);
- pmap_destroy(isa->regs_8bit);
- pmap_destroy(isa->regs_8bit_high);
pmap_destroy(isa->tv_ent);
pmap_destroy(isa->types);
}
-/**
- * Return the number of register classes for this architecture.
- * We report always these:
- * - the general purpose registers
- * - the SSE floating point register set
- * - the virtual floating point registers
- * - the SSE vector register set
- */
-static unsigned ia32_get_n_reg_class(void)
-{
- return N_CLASSES;
-}
-
-/**
- * Return the register class for index i.
- */
-static const arch_register_class_t *ia32_get_reg_class(unsigned i)
-{
- assert(i < N_CLASSES);
- return &ia32_reg_classes[i];
-}
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
const ir_mode *mode)
{
static const arch_register_t *gpreg_param_reg_fastcall[] = {
- &ia32_gp_regs[REG_ECX],
- &ia32_gp_regs[REG_EDX],
+ &ia32_registers[REG_ECX],
+ &ia32_registers[REG_EDX],
NULL
};
static const unsigned MAXNUM_GPREG_ARGS = 3;
static const arch_register_t *gpreg_param_reg_regparam[] = {
- &ia32_gp_regs[REG_EAX],
- &ia32_gp_regs[REG_EDX],
- &ia32_gp_regs[REG_ECX]
+ &ia32_registers[REG_EAX],
+ &ia32_registers[REG_EDX],
+ &ia32_registers[REG_ECX]
};
static const arch_register_t *gpreg_param_reg_this[] = {
- &ia32_gp_regs[REG_ECX],
+ &ia32_registers[REG_ECX],
NULL,
NULL
};
static const arch_register_t *fpreg_sse_param_reg_std[] = {
- &ia32_xmm_regs[REG_XMM0],
- &ia32_xmm_regs[REG_XMM1],
- &ia32_xmm_regs[REG_XMM2],
- &ia32_xmm_regs[REG_XMM3],
- &ia32_xmm_regs[REG_XMM4],
- &ia32_xmm_regs[REG_XMM5],
- &ia32_xmm_regs[REG_XMM6],
- &ia32_xmm_regs[REG_XMM7]
+ &ia32_registers[REG_XMM0],
+ &ia32_registers[REG_XMM1],
+ &ia32_registers[REG_XMM2],
+ &ia32_registers[REG_XMM3],
+ &ia32_registers[REG_XMM4],
+ &ia32_registers[REG_XMM5],
+ &ia32_registers[REG_XMM6],
+ &ia32_registers[REG_XMM7]
};
static const arch_register_t *fpreg_sse_param_reg_this[] = {
assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
- be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
- be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
}
else if (n == 1) {
const arch_register_t *reg;
assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
}
-static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
-{
- (void) block_env;
-
- if (!is_ia32_irn(irn)) {
- return -1;
- }
-
- if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
- || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
- return 0;
-
- return 1;
-}
-
-/**
- * Returns the estimated execution time of an ia32 irn.
- */
-static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
-{
- (void) env;
- return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
-}
-
-list_sched_selector_t ia32_sched_selector;
-
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
- */
-static const list_sched_selector_t *ia32_get_list_sched_selector(
- const void *self, list_sched_selector_t *selector)
-{
- (void) self;
- memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
- ia32_sched_selector.exectime = ia32_sched_exectime;
- ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
- return &ia32_sched_selector;
-}
-
-static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
-{
- (void) self;
- return NULL;
-}
-
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
return bytes;
}
-static const be_execution_unit_t ***ia32_get_allowed_execution_units(
- const ir_node *irn)
-{
- static const be_execution_unit_t *_allowed_units_BRANCH[] = {
- &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
- &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
- NULL,
- };
- static const be_execution_unit_t *_allowed_units_GP[] = {
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
- &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
- NULL,
- };
- static const be_execution_unit_t *_allowed_units_DUMMY[] = {
- &be_machine_execution_units_DUMMY[0],
- NULL,
- };
- static const be_execution_unit_t **_units_callret[] = {
- _allowed_units_BRANCH,
- NULL
- };
- static const be_execution_unit_t **_units_other[] = {
- _allowed_units_GP,
- NULL
- };
- static const be_execution_unit_t **_units_dummy[] = {
- _allowed_units_DUMMY,
- NULL
- };
- const be_execution_unit_t ***ret;
-
- if (is_ia32_irn(irn)) {
- ret = get_ia32_exec_units(irn);
- } else if (is_be_node(irn)) {
- if (be_is_Return(irn)) {
- ret = _units_callret;
- } else if (be_is_Barrier(irn)) {
- ret = _units_dummy;
- } else {
- ret = _units_other;
- }
- }
- else {
- ret = _units_dummy;
- }
-
- return ret;
-}
-
-/**
- * Return the abstract ia32 machine.
- */
-static const be_machine_t *ia32_get_machine(const void *self)
-{
- const ia32_isa_t *isa = self;
- return isa->cpu;
-}
-
/**
* Return irp irgs in the desired order.
*/
* or max(a, b) = a >= b ? a : b
* (Note we only handle float min/max here)
*/
- pnc = get_Proj_proj(sel);
+ pnc = get_Proj_pn_cmp(sel);
switch (pnc) {
case pn_Cmp_Ge:
case pn_Cmp_Gt:
return ia32_get_clobber_register(clobber) != NULL;
}
+static ir_node *ia32_create_set(ir_node *cond)
+{
+ /* ia32-set function produces 8-bit results which have to be converted */
+ ir_node *set = ir_create_mux_set(cond, mode_Bu);
+ ir_node *block = get_nodes_block(set);
+ return new_r_Conv(block, set, mode_Iu);
+}
+
static void ia32_lower_for_target(void)
{
int n_irgs = get_irp_n_irgs();
int i;
lower_mode_b_config_t lower_mode_b_config = {
mode_Iu, /* lowered mode */
- mode_Bu, /* preferred mode for set */
+ ia32_create_set,
0, /* don't lower direct compares */
};
*/
static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
{
- ir_node *st, *p = trampoline;
- ir_mode *mode = get_irn_mode(p);
+ ir_graph *irg = get_irn_irg(block);
+ ir_node *p = trampoline;
+ ir_mode *mode = get_irn_mode(p);
+ ir_node *st;
/* mov ecx,<env> */
- st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, env, 0);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ st = new_r_Store(block, mem, p, env, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
/* jmp <callee> */
- st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, callee, 0);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ st = new_r_Store(block, mem, p, callee, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
return mem;
}
static const ir_settings_arch_dep_t ad = {
1, /* also use subs */
4, /* maximum shifts */
- 31, /* maximum shift amount */
+ 63, /* maximum shift amount */
ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
ia32_init,
ia32_done,
ia32_handle_intrinsics,
- ia32_get_n_reg_class,
- ia32_get_reg_class,
ia32_get_reg_class_for_mode,
ia32_get_call_abi,
- ia32_get_list_sched_selector,
- ia32_get_ilp_sched_selector,
ia32_get_reg_class_alignment,
ia32_get_libfirm_params,
- ia32_get_allowed_execution_units,
- ia32_get_machine,
ia32_get_irg_list,
ia32_mark_remat,
ia32_parse_asm_constraint,
projects / libfirm / blobdiff