#include "config.h"
#endif
-#ifdef _WIN32
+#ifdef HAVE_MALLOC_H
#include <malloc.h>
-#else
+#endif
+
+#ifdef HAVE_ALLOCA_H
#include <alloca.h>
#endif
+#ifdef WITH_LIBCORE
+#include <libcore/lc_opts.h>
+#include <libcore/lc_opts_enum.h>
+#endif /* WITH_LIBCORE */
+
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irprog.h"
#include "ia32_map_regs.h"
#include "ia32_optimize.h"
#include "ia32_x87.h"
+#include "ia32_dbg_stat.h"
#define DEBUG_MODULE "firm.be.ia32.isa"
#undef is_Start
#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
+/* Creates the unique per irg GP NoReg node. */
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
}
+/* Creates the unique per irg FP NoReg node. */
ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
return be_abi_get_callee_save_irn(cg->birg->abi,
USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
const ia32_register_req_t *irn_req;
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
+ FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
if (is_Block(irn) || mode == mode_M || mode == mode_X) {
DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
if (is_Proj(irn)) {
if (pos == -1) {
node_pos = ia32_translate_proj_pos(irn);
char buf[64];
const ia32_irn_ops_t *ops = self;
- if (is_ia32_use_frame(irn) && bias != 0) {
+ if (get_ia32_frame_ent(irn)) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
snprintf(buf, sizeof(buf), "%d", bias);
- add_ia32_am_offs(irn, buf);
- am_flav |= ia32_O;
- set_ia32_am_flavour(irn, am_flav);
+
+ if (get_ia32_op_type(irn) == ia32_Normal) {
+ set_ia32_cnst(irn, buf);
+ }
+ else {
+ add_ia32_am_offs(irn, buf);
+ am_flav |= ia32_O;
+ set_ia32_am_flavour(irn, am_flav);
+ }
}
}
typedef struct {
be_abi_call_flags_bits_t flags;
const arch_isa_t *isa;
+ const arch_env_t *aenv;
ir_graph *irg;
} ia32_abi_env_t;
be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
+ env->aenv = aenv;
env->isa = aenv->isa;
return env;
}
pset_insert_ptr(s, env->isa->bp);
}
+/**
+ * Generate the prologue.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
+ */
static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
{
ia32_abi_env_t *env = self;
- const arch_register_t *frame_reg = env->isa->sp;
- if(!env->flags.try_omit_fp) {
+ if (!env->flags.try_omit_fp) {
int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
ir_node *bl = get_irg_start_block(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *store_bp;
+ /* push ebp */
curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
set_ia32_am_support(store_bp, ia32_am_Dest);
set_ia32_am_flavour(store_bp, ia32_B);
set_ia32_op_type(store_bp, ia32_AddrModeD);
+ set_ia32_ls_mode(store_bp, env->isa->bp->reg_class->mode);
*mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
+
+ /* move esp to ebp */
curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
+ arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+
+ return env->isa->bp;
}
- return frame_reg;
+ return env->isa->sp;
}
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
- if(env->flags.try_omit_fp) {
+ if (env->flags.try_omit_fp) {
+ /* simply remove the stack frame here */
curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
}
else {
ir_node *load_bp;
ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
+ /* copy ebp to esp */
curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
+
+ /* pop ebp */
load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
set_ia32_am_support(load_bp, ia32_am_Source);
set_ia32_am_flavour(load_bp, ia32_B);
set_ia32_ls_mode(load_bp, mode_bp);
curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
*mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
+ arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
+
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_shrink);
}
be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
*/
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- firm_dbg_module_t *old_mod = cg->mod;
+ DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
- cg->mod = firm_dbg_register("firm.be.ia32.transform");
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
+ ia32_register_transformers();
irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
- cg->mod = old_mod;
-
- if (cg->opt.doam) {
+ if (cg->opt & IA32_OPT_DOAM) {
edges_deactivate(cg->irg);
//dead_node_elimination(cg->irg);
edges_activate(cg->irg);
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
+
irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
}
+
+ DEBUG_ONLY(cg->mod = old_mod;)
}
* is not fulfilled.
* Transform Sub into Neg -- Add if IN2 == OUT
*/
-static void ia32_finish_irg_walker(ir_node *irn, void *env) {
+static void ia32_finish_node(ir_node *irn, void *env) {
ia32_code_gen_t *cg = env;
const ia32_register_req_t **reqs;
- const arch_register_t *out_reg, *in_reg;
+ const arch_register_t *out_reg, *in_reg, *in2_reg;
int n_res, i;
- ir_node *copy, *in_node, *block;
+ ir_node *copy, *in_node, *block, *in2_node;
ia32_op_type_t op_tp;
- if (! is_ia32_irn(irn))
- return;
-
- /* AM Dest nodes don't produce any values */
- op_tp = get_ia32_op_type(irn);
- if (op_tp == ia32_AddrModeD)
- return;
-
- reqs = get_ia32_out_req_all(irn);
- n_res = get_ia32_n_res(irn);
- block = get_nodes_block(irn);
-
- /* check all OUT requirements, if there is a should_be_same */
- if (op_tp == ia32_Normal) {
- for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- out_reg = get_ia32_out_reg(irn, i);
- in_node = get_irn_n(irn, reqs[i]->same_pos);
- in_reg = arch_get_irn_register(cg->arch_env, in_node);
-
- /* don't copy ignore nodes */
- if (arch_irn_is(cg->arch_env, in_node, ignore))
- continue;
-
- /* check if in and out register are equal */
- if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
- DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
-
- /* create copy from in register */
- copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
- /* destination is the out register */
- arch_set_irn_register(cg->arch_env, copy, out_reg);
-
- /* insert copy before the node into the schedule */
- sched_add_before(irn, copy);
-
- /* set copy as in */
- set_irn_n(irn, reqs[i]->same_pos, copy);
+ if (is_ia32_irn(irn)) {
+ /* AM Dest nodes don't produce any values */
+ op_tp = get_ia32_op_type(irn);
+ if (op_tp == ia32_AddrModeD)
+ goto end;
+
+ reqs = get_ia32_out_req_all(irn);
+ n_res = get_ia32_n_res(irn);
+ block = get_nodes_block(irn);
+
+ /* check all OUT requirements, if there is a should_be_same */
+ if (op_tp == ia32_Normal && ! is_ia32_Lea(irn)) {
+ for (i = 0; i < n_res; i++) {
+ if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
+ /* get in and out register */
+ out_reg = get_ia32_out_reg(irn, i);
+ in_node = get_irn_n(irn, reqs[i]->same_pos);
+ in_reg = arch_get_irn_register(cg->arch_env, in_node);
+
+ /* don't copy ignore nodes */
+ if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
+ continue;
+
+ /* check if in and out register are equal */
+ if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
+ /* in case of a commutative op: just exchange the in's */
+ /* beware: the current op could be everything, so test for ia32 */
+ /* commutativity first before getting the second in */
+ if (is_ia32_commutative(irn)) {
+ in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
+ in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
+
+ if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
+ set_irn_n(irn, reqs[i]->same_pos, in2_node);
+ set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
+ }
+ else
+ goto insert_copy;
+ }
+ else {
+insert_copy:
+ DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
+ /* create copy from in register */
+ copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
+
+ DBG_OPT_2ADDRCPY(copy);
+
+ /* destination is the out register */
+ arch_set_irn_register(cg->arch_env, copy, out_reg);
+
+ /* insert copy before the node into the schedule */
+ sched_add_before(irn, copy);
+
+ /* set copy as in */
+ set_irn_n(irn, reqs[i]->same_pos, copy);
+ }
+ }
}
}
}
- }
- /* check if there is a sub which need to be transformed */
- ia32_transform_sub_to_neg_add(irn, cg);
+ /* If we have a CondJmp with immediate, we need to */
+ /* check if it's the right operand, otherwise we have */
+ /* to change it, as CMP doesn't support immediate as */
+ /* left operands. */
+ if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
+ long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
+ set_ia32_op_type(irn, ia32_AddrModeD);
+ set_ia32_pncode(irn, pnc);
+ }
+
+ /* check if there is a sub which need to be transformed */
+ ia32_transform_sub_to_neg_add(irn, cg);
- /* transform a LEA into an Add if possible */
- ia32_transform_lea_to_add(irn, cg);
+ /* transform a LEA into an Add if possible */
+ ia32_transform_lea_to_add(irn, cg);
+ }
+end:
/* check for peephole optimization */
ia32_peephole_optimization(irn, cg);
}
+static void ia32_finish_irg_walker(ir_node *block, void *env) {
+ ir_node *irn, *next;
+
+ for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
+ next = sched_next(irn);
+ ia32_finish_node(irn, env);
+ }
+}
+
/**
* Add Copy nodes for not fulfilled should_be_equal constraints
*/
static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
- irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
+ irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
}
}
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ else
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
+ DBG_OPT_RELOAD2LD(irn, new_op);
+
proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
if (sched_point) {
reg = arch_get_irn_register(env->cg->arch_env, irn);
arch_set_irn_register(env->cg->arch_env, new_op, reg);
- exchange(irn, proj);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
+ exchange(irn, proj);
}
/**
}
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ else
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_op_type(new_op, ia32_AddrModeD);
set_ia32_am_flavour(new_op, ia32_B);
- set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_ls_mode(new_op, mode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+ DBG_OPT_SPILL2ST(irn, new_op);
+
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
if (sched_point) {
sched_add_after(sched_point, new_op);
sched_remove(irn);
}
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
+
exchange(irn, proj);
+}
+/**
+ * Fix the mode of Spill/Reload
+ */
+static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
+{
+ if (mode_is_float(mode)) {
+ if (USE_SSE2(cg))
+ mode = mode_D;
+ else
+ mode = mode_E;
+ }
+ else
+ mode = mode_Is;
+ return mode;
}
/**
- * Calls the transform functions for StackParam, Spill and Reload.
+ * Block-Walker: Calls the transform functions Spill and Reload.
*/
-static void ia32_after_ra_walker(ir_node *node, void *env) {
+static void ia32_after_ra_walker(ir_node *block, void *env) {
+ ir_node *node, *prev;
ia32_code_gen_t *cg = env;
ia32_transform_env_t tenv;
- if (is_Block(node))
- return;
-
- tenv.block = get_nodes_block(node);
- tenv.dbg = get_irn_dbg_info(node);
+ tenv.block = block;
tenv.irg = current_ir_graph;
- tenv.irn = node;
- tenv.mod = cg->mod;
- tenv.mode = get_irn_mode(node);
tenv.cg = cg;
-
- /* be_is_StackParam(node) || */
- if (be_is_Reload(node)) {
- transform_to_Load(&tenv);
- }
- else if (be_is_Spill(node)) {
- transform_to_Store(&tenv);
+ DEBUG_ONLY(tenv.mod = cg->mod;)
+
+ /* beware: the schedule is changed here */
+ for (node = sched_last(block); !sched_is_begin(node); node = prev) {
+ prev = sched_prev(node);
+ if (be_is_Reload(node)) {
+ /* we always reload the whole register */
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irn = node;
+ tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
+ transform_to_Load(&tenv);
+ }
+ else if (be_is_Spill(node)) {
+ /* we always spill the whole register */
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irn = node;
+ tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
+ transform_to_Store(&tenv);
+ }
}
}
/**
- * We transform StackParam, Spill and Reload here. This needs to be done before
+ * We transform Spill and Reload here. This needs to be done before
* stack biasing otherwise we would miss the corrected offset for these nodes.
+ *
+ * If x87 instruction should be emitted, run the x87 simulator and patch
+ * the virtual instructions. This must obviously be done after register allocation.
*/
static void ia32_after_ra(void *self) {
ia32_code_gen_t *cg = self;
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
+ irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
/* if we do x87 code generation, rewrite all the virtual instructions and registers */
- if (USE_x87(cg)) {
+ if (cg->used_fp == fp_x87) {
x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
- be_dump(cg->irg, "-x87", dump_ir_extblock_graph_sched);
}
}
static void ia32_codegen(void *self) {
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- FILE *out = cg->out;
-
- if (cg->emit_decls) {
- ia32_gen_decls(cg->out);
- cg->emit_decls = 0;
- }
ia32_finish_irg(irg, cg);
be_dump(irg, "-finished", dump_ir_block_graph_sched);
- ia32_gen_routine(out, irg, cg);
+ ia32_gen_routine(cg->isa->out, irg, cg);
cur_reg_set = NULL;
- pmap_destroy(cg->tv_ent);
- pmap_destroy(cg->types);
+ /* remove it from the isa */
+ cg->isa->cg = NULL;
/* de-allocate code generator */
del_set(cg->reg_set);
free(self);
+
}
-static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
+static void *ia32_cg_init(const be_irg_t *birg);
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
};
/**
- * Initializes the code generator.
+ * Initializes a IA32 code generator.
*/
-static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
+static void *ia32_cg_init(const be_irg_t *birg) {
ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
cg->impl = &ia32_code_gen_if;
cg->irg = birg->irg;
cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.ia32.cg");
- cg->out = F;
cg->arch_env = birg->main_env->arch_env;
- cg->types = pmap_create();
- cg->tv_ent = pmap_create();
+ cg->isa = isa;
cg->birg = birg;
cg->blk_sched = NULL;
+ cg->fp_to_gp = NULL;
+ cg->gp_to_fp = NULL;
cg->fp_kind = isa->fp_kind;
+ cg->used_fp = fp_none;
+
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
- /* set optimizations */
- cg->opt.incdec = 0;
- cg->opt.doam = 1;
- cg->opt.placecnst = 1;
- cg->opt.immops = 1;
- cg->opt.extbb = 1;
+ /* copy optimizations from isa for easier access */
+ cg->opt = isa->opt;
+
+ /* enter it */
+ isa->cg = cg;
#ifndef NDEBUG
if (isa->name_obst_size) {
*
*****************************************************************/
+/**
+ * The template that generates a new ISA object.
+ * Note that this template can be changed by command line
+ * arguments.
+ */
static ia32_isa_t ia32_isa_template = {
&ia32_isa_if, /* isa interface implementation */
&ia32_gp_regs[REG_ESP], /* stack pointer register */
0, /* number of code generator objects so far */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
- fp_sse2, /* use SSE2 unit for fp operations */
+ NULL, /* types */
+ NULL, /* tv_ents */
+ (0 |
+ IA32_OPT_DOAM | /* optimize address mode default: on */
+ IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
+ IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
+ IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
+ arch_pentium_4, /* instruction architecture */
+ arch_pentium_4, /* optimize for architecture */
+ fp_sse2, /* use sse2 unit */
+ NULL, /* current code generator */
#ifndef NDEBUG
NULL, /* name obstack */
0 /* name obst size */
/**
* Initializes the backend ISA.
*/
-static void *ia32_init(void) {
+static void *ia32_init(FILE *file_handle) {
static int inited = 0;
ia32_isa_t *isa;
- if(inited)
+ if (inited)
return NULL;
- isa = xcalloc(1, sizeof(*isa));
+ isa = xmalloc(sizeof(*isa));
memcpy(isa, &ia32_isa_template, sizeof(*isa));
ia32_register_init(isa);
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
-// isa->fp_kind = fp_x87;
+ isa->types = pmap_create();
+ isa->tv_ent = pmap_create();
+ isa->out = file_handle;
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
+ /* patch register names of x87 registers */
+ if (USE_x87(isa)) {
+ ia32_st_regs[0].name = "st";
+ ia32_st_regs[1].name = "st(1)";
+ ia32_st_regs[2].name = "st(2)";
+ ia32_st_regs[3].name = "st(3)";
+ ia32_st_regs[4].name = "st(4)";
+ ia32_st_regs[5].name = "st(5)";
+ ia32_st_regs[6].name = "st(6)";
+ ia32_st_regs[7].name = "st(7)";
+ }
+
#ifndef NDEBUG
- isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
+ isa->name_obst = xmalloc(sizeof(*isa->name_obst));
obstack_init(isa->name_obst);
isa->name_obst_size = 0;
#endif /* NDEBUG */
+ fprintf(isa->out, "\t.intel_syntax\n");
+
inited = 1;
return isa;
static void ia32_done(void *self) {
ia32_isa_t *isa = self;
+ /* emit now all global declarations */
+ ia32_gen_decls(isa->out);
+
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
+ pmap_destroy(isa->tv_ent);
+ pmap_destroy(isa->types);
#ifndef NDEBUG
//printf("name obst size = %d bytes\n", isa->name_obst_size);
* We report always these:
* - the general purpose registers
* - the floating point register set (depending on the unit used for FP)
- * - MMX/SE registers (currently not supported)
+ * - MMX/SSE registers (currently not supported)
*/
static int ia32_get_n_reg_class(const void *self) {
return 2;
int i, ignore_1, ignore_2;
ir_mode **modes;
const arch_register_t *reg;
- be_abi_call_flags_t call_flags;
+ be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
/* set abi flags for calls */
- call_flags.bits.left_to_right = 0;
- call_flags.bits.store_args_sequential = 0;
- call_flags.bits.try_omit_fp = 1;
- call_flags.bits.fp_free = 0;
- call_flags.bits.call_has_imm = 1;
+ call_flags.bits.left_to_right = 0; /* always last arg first on stack */
+ call_flags.bits.store_args_sequential = 0; /* use stores instead of push */
+ /* call_flags.bits.try_omit_fp not changed: can handle both settings */
+ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
+ call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
/* set stack parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
- memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
+// memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
+ memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
+/**
+ * Returns the necessary byte alignment for storing a register of given class.
+ */
+static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+ ir_mode *mode = arch_register_class_mode(cls);
+ int bytes = get_mode_size_bytes(mode);
+
+ if (mode_is_float(mode) && bytes > 8)
+ return 16;
+ return bytes;
+}
+
#ifdef WITH_LIBCORE
+
+/* instruction set architectures. */
+static const lc_opt_enum_int_items_t arch_items[] = {
+ { "386", arch_i386, },
+ { "486", arch_i486, },
+ { "pentium", arch_pentium, },
+ { "586", arch_pentium, },
+ { "pentiumpro", arch_pentium_pro, },
+ { "686", arch_pentium_pro, },
+ { "pentiummmx", arch_pentium_mmx, },
+ { "pentium2", arch_pentium_2, },
+ { "p2", arch_pentium_2, },
+ { "pentium3", arch_pentium_3, },
+ { "p3", arch_pentium_3, },
+ { "pentium4", arch_pentium_4, },
+ { "p4", arch_pentium_4, },
+ { "pentiumm", arch_pentium_m, },
+ { "pm", arch_pentium_m, },
+ { "core", arch_core, },
+ { "k6", arch_k6, },
+ { "athlon", arch_athlon, },
+ { "athlon64", arch_athlon_64, },
+ { "opteron", arch_opteron, },
+ { NULL, 0 }
+};
+
+static lc_opt_enum_int_var_t arch_var = {
+ &ia32_isa_template.arch, arch_items
+};
+
+static lc_opt_enum_int_var_t opt_arch_var = {
+ &ia32_isa_template.opt_arch, arch_items
+};
+
+static const lc_opt_enum_int_items_t fp_unit_items[] = {
+ { "x87" , fp_x87 },
+ { "sse2", fp_sse2 },
+ { NULL, 0 }
+};
+
+static lc_opt_enum_int_var_t fp_unit_var = {
+ &ia32_isa_template.fp_kind, fp_unit_items
+};
+
+static const lc_opt_table_entry_t ia32_options[] = {
+ LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
+ LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
+ LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
+ LC_OPT_ENT_BIT("incdec", "optimize for inc/dec", &ia32_isa_template.opt, IA32_OPT_INCDEC),
+ LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
+ LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
+ LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
+ LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
+ { NULL }
+};
+
+/**
+ * Register command line options for the ia32 backend.
+ *
+ * Options so far:
+ *
+ * ia32-arch=arch create instruction for arch
+ * ia32-opt=arch optimize for run on arch
+ * ia32-fpunit=unit select floating point unit (x87 or SSE2)
+ * ia32-incdec optimize for inc/dec
+ * ia32-noaddrmode do not use address mode
+ * ia32-noplacecnst do not place constants,
+ * ia32-noimmop no operations with immediates
+ * ia32-noextbb do not use extended basic block scheduling
+ */
static void ia32_register_options(lc_opt_entry_t *ent)
{
+ lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
+ lc_opt_add_table(be_grp_ia32, ia32_options);
}
#endif /* WITH_LIBCORE */
const arch_isa_if_t ia32_isa_if = {
-#ifdef WITH_LIBCORE
- ia32_register_options,
-#endif
ia32_init,
ia32_done,
ia32_get_n_reg_class,
ia32_get_call_abi,
ia32_get_irn_handler,
ia32_get_code_generator_if,
- ia32_get_list_sched_selector
+ ia32_get_list_sched_selector,
+ ia32_get_reg_class_alignment,
+#ifdef WITH_LIBCORE
+ ia32_register_options
+#endif
};
projects / libfirm / blobdiff