make transformations before checking 2 addresscode constraints

[libfirm] / ir / be / ia32 / bearch_ia32.c

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 06d6d05..c65aa13 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -327,7 +327,6 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
        ia32_abi_env_t *env              = self;
 
        if (!env->flags.try_omit_fp) {
-               int reg_size         = get_mode_size_bytes(env->isa->bp->reg_class->mode);
                ir_node *bl          = get_irg_start_block(env->irg);
                ir_node *curr_sp     = be_abi_reg_map_get(reg_map, env->isa->sp);
                ir_node *curr_bp     = be_abi_reg_map_get(reg_map, env->isa->bp);
@@ -386,7 +385,6 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
        else {
                const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
                ir_mode *mode_bp = env->isa->bp->reg_class->mode;
-               int reg_size     = get_mode_size_bytes(env->isa->bp->reg_class->mode);
 
                /* gcc always emits a leave at the end of a routine */
                if (1 || ARCH_AMD(isa->opt_arch)) {
@@ -473,6 +471,10 @@ static ir_type *ia32_abi_get_between_type(void *self)
 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
 {
        int cost;
+
+       if(is_Proj(irn))
+         return 0;
+
        switch (get_ia32_irn_opcode(irn)) {
        case iro_ia32_xDiv:
        case iro_ia32_DivMod:
@@ -1009,10 +1011,11 @@ static void ia32_after_ra_walker(ir_node *block, void *env) {
                        transform_to_Load(&tenv);
                }
                else if (be_is_Spill(node)) {
+                       ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
                        /* we always spill the whole register  */
                        tenv.dbg  = get_irn_dbg_info(node);
                        tenv.irn  = node;
-                       tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
+                       tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
                        transform_to_Store(&tenv);
                }
        }
@@ -1036,6 +1039,17 @@ static void ia32_after_ra(void *self) {
        }
 }
 
+/**
+ * Last touchups for the graph before emit
+ */
+static void ia32_finish(void *self) {
+       ia32_code_gen_t *cg = self;
+       ir_graph        *irg = cg->irg;
+
+       ia32_finish_irg(irg, cg);
+       if (cg->dump)
+               be_dump(irg, "-finished", dump_ir_block_graph_sched);
+}
 
 /**
  * Emits the code, closes the output file and frees
@@ -1045,9 +1059,6 @@ static void ia32_codegen(void *self) {
        ia32_code_gen_t *cg = self;
        ir_graph        *irg = cg->irg;
 
-       ia32_finish_irg(irg, cg);
-       if (cg->dump)
-               be_dump(irg, "-finished", dump_ir_block_graph_sched);
        ia32_gen_routine(cg->isa->out, irg, cg);
 
        cur_reg_set = NULL;
@@ -1058,7 +1069,6 @@ static void ia32_codegen(void *self) {
        /* de-allocate code generator */
        del_set(cg->reg_set);
        free(self);
-
 }
 
 static void *ia32_cg_init(const be_irg_t *birg);
@@ -1070,6 +1080,7 @@ static const arch_code_generator_if_t ia32_code_gen_if = {
        ia32_before_sched,   /* before scheduling hook */
        ia32_before_ra,      /* before register allocation hook */
        ia32_after_ra,       /* after register allocation hook */
+       ia32_finish,         /* called before codegen */
        ia32_codegen         /* emit && done */
 };
 
@@ -1296,7 +1307,6 @@ static int ia32_get_n_reg_class(const void *self) {
  * Return the register class for index i.
  */
 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
-       const ia32_isa_t *isa = self;
        assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
        if (i == 0)
                return &ia32_reg_classes[CLASS_ia32_gp];