if (is_ia32_irn(irn)) {
const arch_register_t **slots;
slots = get_ia32_slots(irn);
+ assert(pos < get_ia32_n_res(irn));
reg = slots[pos];
} else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
(void) self;
if (! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_ia32_am_arity(irn) != 2 || /* must be a binary operation TODO is this necessary? */
+ get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
! ia32_is_spillmode_compatible(mode, spillmode) ||
ir_node *mem_proj;
const ir_edge_t *edge;
- ir_fprintf(stderr, "truning back AM in %+F\n", node);
-
load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
set_irn_n(node, n_ia32_mem, new_NoMem());
- if(get_ia32_am_arity(node) == ia32_am_unary) {
- set_irn_n(node, n_ia32_unary_op, load_res);
- } else if(get_ia32_am_arity(node) == ia32_am_binary) {
- if(is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
- assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node)
- || is_ia32_Test(node) || is_ia32_Test8Bit(node));
- set_irn_n(node, n_ia32_binary_left, load_res);
- } else {
+ switch (get_ia32_am_arity(node)) {
+ case ia32_am_unary:
+ set_irn_n(node, n_ia32_unary_op, load_res);
+ break;
+
+ case ia32_am_binary:
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
+ assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
+ is_ia32_Test(node) || is_ia32_Test8Bit(node));
+ set_irn_n(node, n_ia32_binary_left, load_res);
+ } else {
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ }
+ break;
+
+ case ia32_am_ternary:
set_irn_n(node, n_ia32_binary_right, load_res);
- }
- } else if(get_ia32_am_arity(node) == ia32_am_ternary) {
- set_irn_n(node, n_ia32_binary_right, load_res);
+ break;
+
+ default: break;
}
set_irn_n(node, n_ia32_base, noreg);
set_irn_n(node, n_ia32_index, noreg);
block = get_nodes_block(after);
}
- if (type == ia32_AddrModeS) {
- turn_back_am(node);
- } else if (type == ia32_AddrModeD) {
- /* TODO implement this later... */
- panic("found DestAM with flag user %+F this should not happen", node);
- } else {
- assert(type == ia32_Normal);
+ switch (type) {
+ case ia32_AddrModeS: turn_back_am(node); break;
+
+ case ia32_AddrModeD:
+ /* TODO implement this later... */
+ panic("found DestAM with flag user %+F this should not happen", node);
+ break;
+
+ default: assert(type == ia32_Normal); break;
}
copy = exact_copy(node);
- ir_fprintf(stderr, "Remated: %+F\n", copy);
set_nodes_block(copy, block);
sched_add_after(after, copy);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
+ ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
x87_simulate_graph(cg->arch_env, cg->birg);
}
+ /* do peephole optimisations */
+ ia32_peephole_optimization(cg);
+
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
-
- /* do peephole optimisations */
- ia32_peephole_optimization(irg, cg);
}
/**
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
},
- NULL_EMITTER, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* 8bit register names high */
NULL, /* tv_ents */
(0 |
IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
- IA32_OPT_DOAM | /* optimize address mode default: on */
- IA32_OPT_LEA | /* optimize for LEAs default: on */
- IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
- IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
- IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
+ IA32_OPT_CC),
arch_pentium_4, /* instruction architecture */
arch_pentium_4, /* optimize for architecture */
fp_x87, /* floating point mode */
isa->opt &= ~IA32_OPT_INCDEC;
}
- be_emit_init_env(&isa->emit, file_handle);
+ be_emit_init(file_handle);
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
isa->regs_8bit_high = pmap_create();
ia32_handle_intrinsics();
/* needed for the debug support */
- be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
- be_emit_cstring(&isa->emit, ".Ltext0:\n");
- be_emit_write_line(&isa->emit);
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
/* we mark referenced global entities, so we can only emit those which
* are actually referenced. (Note: you mustn't use the type visited flag
ia32_isa_t *isa = self;
/* emit now all global declarations */
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+ be_gas_emit_decls(isa->arch_isa.main_env, 1);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(self);
}
* - the virtual floating point registers
* - the SSE vector register set
*/
-static int ia32_get_n_reg_class(const void *self) {
+static unsigned ia32_get_n_reg_class(const void *self) {
(void) self;
return N_CLASSES;
}
/**
* Return the register class for index i.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
+static const arch_register_class_t *ia32_get_reg_class(const void *self,
+ unsigned i)
{
(void) self;
- assert(i >= 0 && i < N_CLASSES);
+ assert(i < N_CLASSES);
return &ia32_reg_classes[i];
}
cc = cc_cdecl_set;
} else {
cc = get_method_calling_convention(method_type);
- if (get_method_additional_properties(method_type) & mtp_property_private) {
+ if (get_method_additional_properties(method_type) & mtp_property_private
+ && (ia32_isa_template.opt & IA32_OPT_CC)) {
/* set the calling conventions to register parameter */
cc = (cc & ~cc_bits) | cc_reg_param;
}
}
+
+ /* we have to pop the shadow parameter ourself for compound calls */
+ if( (get_method_calling_convention(method_type) & cc_compound_ret)
+ && !(cc & cc_reg_param)) {
+ be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
+ }
+
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- const ir_mode *mode;
+ ir_mode *mode;
const arch_register_t *reg = NULL;
tp = get_method_param_type(method_type, i);
be_abi_call_param_reg(abi, i, reg);
++regnum;
} else {
- be_abi_call_param_stack(abi, i, 4, 0, 0);
+ /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
+ * movl has a shorter opcode than mov[sz][bw]l */
+ ir_mode *load_mode = mode;
+ if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
+ be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
}
}
(void)i;
(void)j;
-#if 1
+ /* we can't handle psis with 64bit compares yet */
if(is_Proj(sel)) {
ir_node *pred = get_Proj_pred(sel);
if(is_Cmp(pred)) {
ir_node *left = get_Cmp_left(pred);
ir_mode *cmp_mode = get_irn_mode(left);
- if(mode_is_float(cmp_mode))
+ if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
return 0;
}
}
-#endif
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
arch_costs = &k6_cost;
break;
case arch_athlon:
+ case arch_athlon_xp:
case arch_athlon_64:
case arch_opteron:
arch_costs = &athlon_cost;
{ "core", arch_core, },
{ "k6", arch_k6, },
{ "athlon", arch_athlon, },
+ { "athlon-xp", arch_athlon_xp, },
{ "athlon64", arch_athlon_64, },
{ "opteron", arch_opteron, },
{ "generic", arch_generic, },
LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
- LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
- LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
- LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
- LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
- LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
+ LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
LC_OPT_LAST
};
projects / libfirm / blobdiff