+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
+
/**
- * This is the main ia32 firm backend driver.
- * @author Christian Wuerdig
- * $Id$
+ * @file
+ * @brief This is the main ia32 firm backend driver.
+ * @author Christian Wuerdig
+ * @version $Id$
*/
#ifdef HAVE_CONFIG_H
-#include <config.h>
-#endif
-
-#ifdef HAVE_MALLOC_H
-#include <malloc.h>
-#endif
-
-#ifdef HAVE_ALLOCA_H
-#include <alloca.h>
+#include "config.h"
#endif
#include <libcore/lc_opts.h>
#include <math.h>
#include "pseudo_irg.h"
+#include "irarch.h"
#include "irgwalk.h"
#include "irprog.h"
#include "irprintf.h"
#include "pset.h"
#include "debug.h"
#include "error.h"
+#include "xmalloc.h"
+#include "irtools.h"
#include "../beabi.h"
-#include "../beirg.h"
+#include "../beirg_t.h"
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
#include "../be_t.h"
#include "../beirgmod.h"
#include "../be_dbgout.h"
#include "../bespillslots.h"
#include "../bemodule.h"
#include "../begnuas.h"
+#include "../bestate.h"
+#include "../beflags.h"
#include "bearch_ia32_t.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
#include "ia32_util.h"
+#include "ia32_fpu.h"
+
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/* TODO: ugly */
static set *cur_reg_set = NULL;
+ir_mode *mode_fpcw = NULL;
+ia32_code_gen_t *ia32_current_cg = NULL;
+
+/**
+ * The environment for the intrinsic mapping.
+ */
+static ia32_intrinsic_env_t intrinsic_env = {
+ NULL, /* the isa */
+ NULL, /* the irg, these entities belong to */
+ NULL, /* entity for first div operand (move into FPU) */
+ NULL, /* entity for second div operand (move into FPU) */
+ NULL, /* entity for converts ll -> d */
+ NULL, /* entity for converts d -> ll */
+ NULL, /* entity for __divdi3 library call */
+ NULL, /* entity for __moddi3 library call */
+ NULL, /* entity for __udivdi3 library call */
+ NULL, /* entity for __umoddi3 library call */
+ NULL, /* bias value for conversion from float to unsigned 64 */
+};
+
+
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
create_const_node_func func,
- arch_register_t* reg)
+ const arch_register_t* reg)
{
ir_node *block, *res;
- ir_node *in[1];
- ir_node *startnode;
- ir_node *keep;
if(*place != NULL)
return *place;
arch_set_irn_register(cg->arch_env, res, reg);
*place = res;
- /* keep the node so it isn't accidently removed when unused ... */
- in[0] = res;
- keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
-
- /* schedule the node if we already have a scheduled program */
- startnode = get_irg_start(cg->irg);
- if(sched_is_scheduled(startnode)) {
- sched_add_after(startnode, res);
- sched_add_after(res, keep);
- }
+ add_irn_dep(get_irg_end(cg->irg), res);
+ /* add_irn_dep(get_irg_start(cg->irg), res); */
return res;
}
&ia32_xmm_regs[REG_XMM_UKNWN]);
}
+ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
+ return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
+ &ia32_fp_cw_regs[REG_FPCW]);
+}
+
/**
* Returns gp_noreg or fp_noreg, depending in input requirements.
*/
static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
const ir_node *node,
- int pos) {
+ int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
+ (void) self;
if (is_Block(node) || mode == mode_X) {
return arch_no_register_req;
return arch_no_register_req;
}
-static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void ia32_set_irn_reg(const void *self, ir_node *irn,
+ const arch_register_t *reg)
+{
int pos = 0;
+ (void) self;
if (get_irn_mode(irn) == mode_X) {
return;
}
}
-static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *ia32_get_irn_reg(const void *self,
+ const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
+ (void) self;
if (is_Proj(irn)) {
if (is_ia32_irn(irn)) {
const arch_register_t **slots;
slots = get_ia32_slots(irn);
+ assert(pos < get_ia32_n_res(irn));
reg = slots[pos];
} else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
arch_irn_class_t classification = arch_irn_class_normal;
+ (void) self;
irn = skip_Proj_const(irn);
if (! is_ia32_irn(irn))
return classification & ~arch_irn_class_normal;
- if (is_ia32_Cnst(irn))
- classification |= arch_irn_class_const;
-
if (is_ia32_Ld(irn))
classification |= arch_irn_class_load;
- if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+ if (is_ia32_St(irn))
classification |= arch_irn_class_store;
if (is_ia32_need_stackent(irn))
static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
arch_irn_flags_t flags = arch_irn_flags_none;
+ (void) self;
if (is_Unknown(irn))
return arch_irn_flags_ignore;
} ia32_abi_env_t;
static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
+ (void) self;
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+ (void) self;
set_ia32_frame_ent(irn, ent);
}
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
- ia32_am_flavour_t am_flav;
-
if (is_ia32_Pop(irn)) {
int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
if (omit_fp) {
}
}
- am_flav = get_ia32_am_flavour(irn);
- am_flav |= ia32_O;
- set_ia32_am_flavour(irn, am_flav);
-
add_ia32_am_offs_int(irn, bias);
}
}
-static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
- if(is_Proj(irn)) {
- long proj = get_Proj_proj(irn);
- ir_node *pred = get_Proj_pred(irn);
+static int ia32_get_sp_bias(const void *self, const ir_node *node)
+{
+ (void) self;
- if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
- return 4;
- if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
- return -4;
- }
+ if (is_ia32_Push(node))
+ return 4;
+
+ if (is_ia32_Pop(node))
+ return -4;
return 0;
}
pset_insert_ptr(s, env->isa->bp);
}
-static void get_regparams_startbarrier(ir_graph *irg, ir_node **regparams, ir_node **startbarrier)
-{
- const ir_edge_t *edge;
- ir_node *start_block = get_irg_start_block(irg);
-
- *regparams = NULL;
- *startbarrier = NULL;
- foreach_out_edge(start_block, edge) {
- ir_node *src = get_edge_src_irn(edge);
-
- if(be_is_RegParams(src)) {
- *regparams = src;
- if(*startbarrier != NULL)
- return;
- }
- if(be_is_Barrier(src)) {
- *startbarrier = src;
- if(*regparams != NULL)
- return;
- }
- }
-
- panic("Couldn't find regparams and startbarrier!");
-}
-
-static void add_fpu_edges(be_irg_t *birg)
-{
- ir_graph *irg = be_get_birg_irg(birg);
- ir_node *regparams;
- ir_node *startbarrier;
- ir_node *fp_cw_reg;
- ir_node *end_block;
- const arch_env_t *arch_env = birg->main_env->arch_env;
- const arch_register_t *reg = &ia32_fp_cw_regs[REG_FPCW];
- int i, arity;
- int pos;
-
- get_regparams_startbarrier(irg, ®params, &startbarrier);
-
- fp_cw_reg = be_RegParams_append_out_reg(regparams, arch_env, reg);
-
- fp_cw_reg = be_Barrier_append_node(startbarrier, fp_cw_reg);
- pos = get_Proj_proj(fp_cw_reg);
- be_set_constr_single_reg(startbarrier, BE_OUT_POS(pos), reg);
- arch_set_irn_register(arch_env, fp_cw_reg, reg);
-
- /* search returns */
- end_block = get_irg_end_block(irg);
- arity = get_irn_arity(end_block);
- for(i = 0; i < arity; ++i) {
- int i2, arity2;
- ir_node *ret = get_irn_n(end_block, i);
- ir_node *end_barrier = NULL;
- ir_node *fp_cw_after_end_barrier;
- if(!be_is_Return(ret))
- continue;
-
- /* search the barrier before the return */
- arity2 = get_irn_arity(ret);
- for(i2 = 0; i2 < arity2; i2++) {
- ir_node *proj = get_irn_n(ret, i2);
-
- if(!is_Proj(proj))
- continue;
-
- end_barrier = get_Proj_pred(proj);
- if(!be_is_Barrier(end_barrier))
- continue;
- break;
- }
- assert(end_barrier != NULL);
-
- /* add fp_cw to the barrier */
- fp_cw_after_end_barrier = be_Barrier_append_node(end_barrier, fp_cw_reg);
- pos = get_Proj_proj(fp_cw_after_end_barrier);
- be_set_constr_single_reg(end_barrier, BE_OUT_POS(pos), reg);
- arch_set_irn_register(arch_env, fp_cw_after_end_barrier, reg);
-
- /* and append it to the return node */
- be_Return_append_node(ret, fp_cw_after_end_barrier);
- }
-}
-
-
-#if 0
-static unsigned count_callee_saves(ia32_code_gen_t *cg)
-{
- unsigned callee_saves = 0;
- int c, num_reg_classes;
- arch_isa_if_t *isa;
-
- num_reg_classes = arch_isa_get_n_reg_class(isa);
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
- arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
-
- num_registers = arch_register_class_n_regs(regclass);
- for(r = 0; r < num_registers; ++r) {
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(arch_register_type_is(reg, callee_save))
- callee_saves++;
- }
- }
-
- return callee_saves;
-}
-
-static void create_callee_save_regprojs(ia32_code_gen_t *cg, ir_node *regparams)
-{
- int c, num_reg_classes;
- arch_isa_if_t *isa;
- long n = 0;
-
- num_reg_classes = arch_isa_get_n_reg_class(isa);
- cg->initial_regs = obstack_alloc(cg->obst,
- num_reg_classes * sizeof(cg->initial_regs[0]));
-
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
- ir_node **initial_regclass;
- arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
-
- num_registers = arch_register_class_n_regs(regclass);
- initial_regclass = obstack_alloc(num_registers * sizeof(initial_regclass[0]));
- for(r = 0; r < num_registers; ++r) {
- ir_node *proj;
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(!arch_register_type_is(reg, callee_save))
- continue;
-
- proj = new_r_Proj(irg, start_block, regparams, n);
- be_set_constr_single_reg(regparams, n, reg);
- arch_set_irn_register(cg->arch_env, proj, reg);
-
- initial_regclass[r] = proj;
- n++;
- }
- cg->initial_regs[c] = initial_regclass;
- }
-}
-
-static void callee_saves_obstack_grow(ia32_code_gen_t *cg)
-{
- int c, num_reg_classes;
- arch_isa_if_t *isa;
-
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
-
- num_registers = arch_register_class_n_regs(regclass);
- for(r = 0; r < num_registers; ++r) {
- ir_node *proj;
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(!arch_register_type_is(reg, callee_save))
- continue;
-
- proj = cg->initial_regs[c][r];
- obstack_ptr_grow(cg->obst, proj);
- }
- }
-}
-
-static unsigned count_parameters_in_regs(ia32_code_gen_t *cg)
-{
- return 0;
-}
-
-static void ia32_gen_prologue(ia32_code_gen_t *cg)
-{
- ir_graph *irg = cg->irg;
- ir_node *start_block = get_irg_start_block(irg);
- ir_node *sp;
- ir_node *regparams;
- int n_regparams_out;
-
- /* Create the regparams node */
- n_regparams_out = count_callee_saves(cg) + count_parameters_in_regs(cg);
- regparams = be_new_RegParams(irg, start_block, n_regparams_out);
-
- create_callee_save_regprojs(cg, regparams);
-
- /* Setup the stack */
- if(!omit_fp) {
- ir_node *bl = get_irg_start_block(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *push;
-
- /* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
- curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
- *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
-
- /* the push must have SP out register */
- arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
- set_ia32_flags(push, arch_irn_flags_ignore);
-
- /* move esp to ebp */
- curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
- be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
- arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
- be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- /* beware: the copy must be done before any other sp use */
- curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
- be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
- arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
- be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
- be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
- }
-
- sp = be_new_IncSP(sp, irg, start_block, initialsp, BE_STACK_FRAME_SIZE_EXPAND);
- set_irg_frame(irg, sp);
-}
-
-static void ia32_gen_epilogue(ia32_code_gen_t *cg)
-{
- int n_callee_saves = count_callee_saves(cg);
- int n_results_regs = 0;
- int barrier_size;
- ir_node *barrier;
- ir_node *end_block = get_irg_end_block(irg);
- ir_node **in;
-
- /* We have to make sure that all reloads occur before the stack frame
- gets destroyed, so we create a barrier for all callee-save and return
- values here */
- barrier_size = n_callee_saves + n_results_regs;
- barrier = be_new_Barrier(irg, end_block, barrier_size,
-
- /* simply remove the stack frame here */
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
- add_irn_dep(curr_sp, *mem);
-}
-#endif
-
/**
* Generate the routine prologue.
*
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *push;
+ /* ALL nodes representing bp must be set to ignore. */
+ be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
+
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
} else {
const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
ia32_code_gen_t *cg = isa->cg;
- ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ ir_graph *irg = current_ir_graph;
- /* gcc always emits a leave at the end of a routine */
- if (1 || ARCH_AMD(isa->opt_arch)) {
+ if (ARCH_AMD(isa->opt_arch)) {
ir_node *leave;
/* leave */
- leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
+ leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
set_ia32_flags(leave, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
- curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+ curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
} else {
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *pop;
+ /* the old SP is not needed anymore (kill the proj) */
+ assert(is_Proj(curr_sp));
+ be_kill_node(curr_sp);
+
/* copy ebp to esp */
- curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
+ curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
set_ia32_flags(pop, arch_irn_flags_ignore);
- curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
- curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+ curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
+ curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
- *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
+ *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
}
arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
cost += 150;
}
else if (is_ia32_CopyB_i(irn)) {
- int size = get_tarval_long(get_ia32_Immop_tarval(irn));
+ int size = get_ia32_pncode(irn);
cost = 20 + (int)ceil((4/3) * size);
if (ARCH_INTEL(ops->cg->arch))
cost += 150;
/* in case of address mode operations add additional cycles */
else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
/*
- In case of stack access add 5 cycles (we assume stack is in cache),
- other memory operations cost 20 cycles.
+ In case of stack access and access to fixed addresses add 5 cycles
+ (we assume they are in cache), other memory operations cost 20
+ cycles.
*/
- cost += is_ia32_use_frame(irn) ? 5 : 20;
+ if(is_ia32_use_frame(irn) ||
+ (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
+ is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
+ cost += 5;
+ } else {
+ cost += 20;
+ }
}
return cost;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
dbg_info *dbg;
+ (void) self;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
return NULL;
/* operand must always be a real operand (not base, index or mem) */
- if (i != 2 && i != 3)
+ if (i != n_ia32_binary_left && i != n_ia32_binary_right)
return NULL;
/* we don't invert address mode operations */
if (get_ia32_op_type(irn) != ia32_Normal)
return NULL;
+ /* TODO: adjust for new immediates... */
+ ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
+ irn);
+ return NULL;
+
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
+#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
+#endif
break;
case iro_ia32_Sub:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
- if (i == 2) {
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
+ if (i == n_ia32_binary_left) {
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Xor:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
}
/**
- * Checks wether an addressmode reload for a node with mode mode is compatible
+ * Checks whether an addressmode reload for a node with mode mode is compatible
* with a spillslot of mode spill_mode
*/
static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
ir_node *op = get_irn_n(irn, i);
const ir_mode *mode = get_irn_mode(op);
const ir_mode *spillmode = get_spill_mode(op);
-
- if (! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_irn_arity(irn) != 5 || /* must be a binary operation */
- get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
- ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
- ! ia32_is_spillmode_compatible(mode, spillmode) ||
- (i != 2 && i != 3) || /* a "real" operand position must be requested */
- (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
- is_ia32_use_frame(irn)) /* must not already use frame */
+ (void) self;
+
+ if (! is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
+ ! ia32_is_spillmode_compatible(mode, spillmode) ||
+ (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
+ is_ia32_use_frame(irn)) /* must not already use frame */
return 0;
+ if (i == n_ia32_binary_left) {
+ const arch_register_req_t *req;
+ if(!is_ia32_commutative(irn))
+ return 0;
+ /* we can't swap left/right for limited registers
+ * (As this (currently) breaks constraint handling copies)
+ */
+ req = get_ia32_in_req(irn, n_ia32_binary_left);
+ if(req->type & arch_register_req_type_limited) {
+ return 0;
+ }
+ }
+
return 1;
}
-static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
+static void ia32_perform_memory_operand(const void *self, ir_node *irn,
+ ir_node *spill, unsigned int i)
+{
const ia32_irn_ops_t *ops = self;
ia32_code_gen_t *cg = ops->cg;
assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
- if (i == 2) {
- ir_node *tmp = get_irn_n(irn, 3);
- set_irn_n(irn, 3, get_irn_n(irn, 2));
- set_irn_n(irn, 2, tmp);
+ if (i == n_ia32_binary_left) {
+ ia32_swap_left_right(irn);
}
- set_ia32_am_support(irn, ia32_am_Source);
set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
- set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
- set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
- set_irn_n(irn, 4, spill);
+ set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
+ set_irn_n(irn, n_ia32_mem, spill);
- //FIXME DBG_OPT_AM_S(reload, irn);
+ /* immediates are only allowed on the right side */
+ if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
+ ia32_swap_left_right(irn);
+ }
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
ia32_abi_get_between_type,
ia32_abi_dont_save_regs,
ia32_abi_prologue,
- ia32_abi_epilogue,
+ ia32_abi_epilogue
};
/* fill register allocator interface */
* |___/
**************************************************/
+static void ia32_before_abi(void *self) {
+ ia32_code_gen_t *cg = self;
+
+ ir_lower_mode_b(cg->irg, mode_Iu, 0);
+ if(cg->dump)
+ be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+}
+
/**
* Transforms the standard firm graph into
* an ia32 firm graph
*/
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
+ /* do local optimisations */
+ optimize_graph_df(cg->irg);
+
+ /* TODO: we often have dead code reachable through out-edges here. So for
+ * now we rebuild edges (as we need correct user count for code selection)
+ */
+#if 1
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+#endif
- /* transform psi condition trees */
- ia32_pre_transform_phase(cg);
+ if(cg->dump)
+ be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
- /* transform all remaining nodes */
+ /* transform nodes into assembler instructions */
ia32_transform_graph(cg);
- add_fpu_edges(cg->birg);
- // Matze: disabled for now. Because after transformation start block has no
- // self-loop anymore so it might be merged with its successor block. This
- // will bring several nodes to the startblock which sometimes get scheduled
- // before the initial IncSP/Barrier
- //local_optimize_graph(cg->irg);
+ /* do local optimisations (mainly CSE) */
+ optimize_graph_df(cg->irg);
if (cg->dump)
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
/* optimize address mode */
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
- ia32_optimize_addressmode(cg);
+ ia32_optimize_graph(cg);
if (cg->dump)
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
if (cg->dump)
be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
-
- DEBUG_ONLY(cg->mod = old_mod;)
}
/**
* Dummy functions for hooks we don't need but which must be filled.
*/
static void ia32_before_sched(void *self) {
+ (void) self;
}
-static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
- int i, arity;
- ir_mode *mode;
- ir_node *mem_proj = NULL;
+static void turn_back_am(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *mem = get_irn_n(node, n_ia32_mem);
+ ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
+ ir_node *load;
+ ir_node *load_res;
+ ir_node *mem_proj;
+ const ir_edge_t *edge;
- if (is_Block(irn))
- return;
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+ load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
- mode = get_irn_mode(irn);
+ ia32_copy_am_attrs(load, node);
+ set_irn_n(node, n_ia32_mem, new_NoMem());
- /* check if we already saw this node or the node has more than one user */
- if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
- return;
- };
+ switch (get_ia32_am_arity(node)) {
+ case ia32_am_unary:
+ set_irn_n(node, n_ia32_unary_op, load_res);
+ break;
- /* mark irn visited */
- bitset_add_irn(already_visited, irn);
+ case ia32_am_binary:
+ if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
+ assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
+ is_ia32_Test(node) || is_ia32_Test8Bit(node));
+ set_irn_n(node, n_ia32_binary_left, load_res);
+ } else {
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ }
+ break;
- /* non-Tuple nodes with one user: ok, return */
- if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
- return;
- }
+ case ia32_am_ternary:
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ break;
- /* tuple node has one user which is not the mem proj-> ok */
- if (mode == mode_T && get_irn_n_edges(irn) == 1) {
- mem_proj = ia32_get_proj_for_mode(irn, mode_M);
- if (mem_proj == NULL) {
- return;
+ default: break;
+ }
+ set_irn_n(node, n_ia32_base, noreg);
+ set_irn_n(node, n_ia32_index, noreg);
+ set_ia32_am_offs_int(node, 0);
+ set_ia32_am_sc(node, NULL);
+ set_ia32_am_scale(node, 0);
+ clear_ia32_am_sc_sign(node);
+
+ /* rewire mem-proj */
+ if(get_irn_mode(node) == mode_T) {
+ mem_proj = NULL;
+ foreach_out_edge(node, edge) {
+ ir_node *out = get_edge_src_irn(edge);
+ if(get_Proj_proj(out) == pn_ia32_mem) {
+ mem_proj = out;
+ break;
+ }
}
- }
-
- arity = get_irn_arity(irn);
- for (i = 0; i < arity; ++i) {
- ir_node *pred = get_irn_n(irn, i);
- /* do not follow memory edges or we will accidentally remove stores */
- if (get_irn_mode(pred) == mode_M) {
- if(mem_proj != NULL) {
- edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
- mem_proj = NULL;
- }
- continue;
+ if(mem_proj != NULL) {
+ set_Proj_pred(mem_proj, load);
+ set_Proj_proj(mem_proj, pn_ia32_Load_M);
}
+ }
- set_irn_n(irn, i, new_Bad());
+ set_ia32_op_type(node, ia32_Normal);
+ if(sched_is_scheduled(node))
+ sched_add_before(node, load);
+}
- /*
- The current node is about to be removed: if the predecessor
- has only this node as user, it need to be removed as well.
- */
- if (get_irn_n_edges(pred) <= 1)
- remove_unused_nodes(pred, already_visited);
- }
+static ir_node *flags_remat(ir_node *node, ir_node *after)
+{
+ /* we should turn back source address mode when rematerializing nodes */
+ ia32_op_type_t type = get_ia32_op_type(node);
+ ir_node *block;
+ ir_node *copy;
- // we need to set the presd to Bad again to also get the memory edges
- arity = get_irn_arity(irn);
- for (i = 0; i < arity; ++i) {
- set_irn_n(irn, i, new_Bad());
+ if(is_Block(after)) {
+ block = after;
+ } else {
+ block = get_nodes_block(after);
}
- if (sched_is_scheduled(irn)) {
- sched_remove(irn);
+ switch (type) {
+ case ia32_AddrModeS: turn_back_am(node); break;
+
+ case ia32_AddrModeD:
+ /* TODO implement this later... */
+ panic("found DestAM with flag user %+F this should not happen", node);
+ break;
+
+ default: assert(type == ia32_Normal); break;
}
-}
-static void remove_unused_loads_walker(ir_node *irn, void *env) {
- bitset_t *already_visited = env;
- if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
- remove_unused_nodes(irn, env);
+ copy = exact_copy(node);
+ set_nodes_block(copy, block);
+ sched_add_after(after, copy);
+
+ return copy;
}
/**
* simulator and the emitter.
*/
static void ia32_before_ra(void *self) {
- ia32_code_gen_t *cg = self;
- bitset_t *already_visited = bitset_irg_alloca(cg->irg);
+ ia32_code_gen_t *cg = self;
+
+ /* setup fpu rounding modes */
+ ia32_setup_fpu_mode(cg);
+
+ /* fixup flags */
+ be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
+ &flags_remat);
- /*
- Handle special case:
- There are sometimes unused loads, only pinned by memory.
- We need to remove those Loads and all other nodes which won't be used
- after removing the Load from schedule.
- */
- irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
+ ia32_add_missing_keeps(cg);
}
if (mode_is_float(spillmode)) {
if (USE_SSE2(cg))
- new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
else
- new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
// Reload 128 bit sse registers
else
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
- set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
if (sched_point) {
sched_add_after(sched_point, new_op);
- sched_add_after(new_op, proj);
-
sched_remove(node);
}
if (mode_is_float(mode)) {
if (USE_SSE2(cg))
- store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
else
- store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else if (get_mode_size_bits(mode) == 128) {
+ store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
+ } else if (get_mode_size_bits(mode) == 128) {
// Spill 128 bit SSE registers
- store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else if (get_mode_size_bits(mode) == 8) {
- store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else {
- store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
+ } else if (get_mode_size_bits(mode) == 8) {
+ store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
+ } else {
+ store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
}
- set_ia32_am_support(store, ia32_am_Dest);
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
+ ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
- set_ia32_am_flavour(push, ia32_B);
set_ia32_ls_mode(push, mode_Is);
sched_add_before(schedpoint, push);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
+ ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
- set_ia32_am_flavour(pop, ia32_am_OB);
set_ia32_ls_mode(pop, mode_Is);
sched_add_before(schedpoint, pop);
return pop;
}
-static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
+static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
ir_graph *irg = get_irn_irg(node);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
arch_set_irn_register(cg->arch_env, sp, spreg);
- sched_add_before(schedpoint, sp);
return sp;
}
// create pushs
for(i = 0; i < arity; ++i) {
- ir_entity *ent = be_get_MemPerm_in_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(inent);
int entbits = get_type_size_bits(enttype);
+ int entbits2 = get_type_size_bits(get_entity_type(outent));
ir_node *mem = get_irn_n(node, i + 1);
ir_node *push;
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- push = create_push(cg, node, node, sp, mem, ent);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
+ push = create_push(cg, node, node, sp, mem, inent);
+ sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
if(entbits == 64) {
// add another push after the first one
- push = create_push(cg, node, node, sp, mem, ent);
+ push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
- sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
+ sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
}
set_irn_n(node, i, new_Bad());
// create pops
for(i = arity - 1; i >= 0; --i) {
- ir_entity *ent = be_get_MemPerm_out_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(outent);
int entbits = get_type_size_bits(enttype);
-
+ int entbits2 = get_type_size_bits(get_entity_type(inent));
ir_node *pop;
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- pop = create_pop(cg, node, node, sp, ent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
+ pop = create_pop(cg, node, node, sp, outent);
+ sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
if(entbits == 64) {
add_ia32_am_offs_int(pop, 4);
// add another pop after the first one
- pop = create_pop(cg, node, node, sp, ent);
- sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
+ pop = create_pop(cg, node, node, sp, outent);
+ sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
}
pops[i] = pop;
assert(p < arity);
set_Proj_pred(proj, pops[p]);
- set_Proj_proj(proj, 3);
+ set_Proj_proj(proj, pn_ia32_Pop_M);
}
// remove memperm
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) {
if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = get_mode_size_bytes(mode);
+ const ir_mode *mode = get_ia32_ls_mode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int align = get_mode_size_bytes(mode);
+
+ if(attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ }
+ if(attr->data.need_32bit_stackent) {
+ mode = mode_Is;
+ }
be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
+ } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
+ || is_ia32_vfld(node)) {
const ir_mode *mode = get_ia32_ls_mode(node);
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_SetST0(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
+ } else if(is_ia32_FldCW(node)) {
+ const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
} else {
#ifndef NDEBUG
- if(!is_ia32_Store(node)
- && !is_ia32_xStore(node)
- && !is_ia32_xStoreSimple(node)
- && !is_ia32_vfist(node)
- && !is_ia32_GetST0(node)) {
- assert(0);
- }
+ assert(is_ia32_St(node) ||
+ is_ia32_xStoreSimple(node) ||
+ is_ia32_vfst(node) ||
+ is_ia32_vfist(node) ||
+ is_ia32_FnstCW(node));
#endif
}
}
be_free_frame_entity_coalescer(fec_env);
irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
-
- ia32_finish_irg(irg, cg);
}
/**
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- /* if we do x87 code generation, rewrite all the virtual instructions and registers */
- if (cg->used_fp == fp_x87 || cg->force_sim) {
+ ia32_finish_irg(irg, cg);
+
+ /* we might have to rewrite x87 virtual registers */
+ if (cg->do_x87_sim) {
x87_simulate_graph(cg->arch_env, cg->birg);
}
+ /* do peephole optimisations */
+ ia32_peephole_optimization(cg);
+
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
-
- /* do peephole optimisations */
- ia32_peephole_optimization(irg, cg);
}
/**
/* remove it from the isa */
cg->isa->cg = NULL;
+ assert(ia32_current_cg == cg);
+ ia32_current_cg = NULL;
+
/* de-allocate code generator */
del_set(cg->reg_set);
free(cg);
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
- NULL, /* before abi introduce hook */
+ ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
NULL, /* spill */
ia32_before_sched, /* before scheduling hook */
cg->birg = birg;
cg->blk_sched = NULL;
cg->fp_kind = isa->fp_kind;
- cg->used_fp = fp_none;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
-
/* copy optimizations from isa for easier access */
cg->opt = isa->opt;
cg->arch = isa->arch;
ia32_irn_ops.cg = cg;
+ assert(ia32_current_cg == NULL);
+ ia32_current_cg = cg;
+
return (arch_code_generator_t *)cg;
}
* Set output modes for GCC
*/
static const tarval_mode_info mo_integer = {
- TVO_DECIMAL,
- NULL,
+ TVO_HEX,
+ "0x",
NULL,
};
&ia32_gp_regs[REG_EBP], /* base pointer register */
-1, /* stack direction */
NULL, /* main environment */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
},
- {}, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
+ NULL, /* 8bit register names high */
NULL, /* types */
NULL, /* tv_ents */
(0 |
IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
- IA32_OPT_DOAM | /* optimize address mode default: on */
- IA32_OPT_LEA | /* optimize for LEAs default: on */
- IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
- IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
- IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
+ IA32_OPT_CC),
arch_pentium_4, /* instruction architecture */
arch_pentium_4, /* optimize for architecture */
- fp_sse2, /* use sse2 unit */
+ fp_x87, /* floating point mode */
NULL, /* current code generator */
#ifndef NDEBUG
NULL, /* name obstack */
#endif
};
+static void set_arch_costs(enum cpu_support arch);
+
/**
* Initializes the backend ISA.
*/
if (inited)
return NULL;
+ inited = 1;
set_tarval_output_modes();
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ia32_isa_template, sizeof(*isa));
- ia32_register_init(isa);
+ if(mode_fpcw == NULL) {
+ mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ }
+
+ ia32_register_init();
ia32_create_opcodes();
- ia32_register_copy_attr_func();
+
+ set_arch_costs(isa->opt_arch);
if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
(ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
isa->opt &= ~IA32_OPT_INCDEC;
}
- be_emit_init_env(&isa->emit, file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->types = pmap_create();
- isa->tv_ent = pmap_create();
- isa->cpu = ia32_init_machine_description();
+ be_emit_init(file_handle);
+ isa->regs_16bit = pmap_create();
+ isa->regs_8bit = pmap_create();
+ isa->regs_8bit_high = pmap_create();
+ isa->types = pmap_create();
+ isa->tv_ent = pmap_create();
+ isa->cpu = ia32_init_machine_description();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
-
- /* patch register names of x87 registers */
- ia32_st_regs[0].name = "st";
- ia32_st_regs[1].name = "st(1)";
- ia32_st_regs[2].name = "st(2)";
- ia32_st_regs[3].name = "st(3)";
- ia32_st_regs[4].name = "st(4)";
- ia32_st_regs[5].name = "st(5)";
- ia32_st_regs[6].name = "st(6)";
- ia32_st_regs[7].name = "st(7)";
+ ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
#ifndef NDEBUG
isa->name_obst = xmalloc(sizeof(*isa->name_obst));
obstack_init(isa->name_obst);
#endif /* NDEBUG */
+ /* enter the ISA object into the intrinsic environment */
+ intrinsic_env.isa = isa;
ia32_handle_intrinsics();
/* needed for the debug support */
- be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
- be_emit_cstring(&isa->emit, ".Ltext0:\n");
- be_emit_write_line(&isa->emit);
+ be_gas_emit_switch_section(GAS_SECTION_TEXT);
+ be_emit_cstring(".Ltext0:\n");
+ be_emit_write_line();
- inited = 1;
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
return isa;
}
ia32_isa_t *isa = self;
/* emit now all global declarations */
- be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env);
+ be_gas_emit_decls(isa->arch_isa.main_env, 1);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
+ pmap_destroy(isa->regs_8bit_high);
pmap_destroy(isa->tv_ent);
pmap_destroy(isa->types);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
- be_emit_destroy_env(&isa->emit);
+ be_emit_exit();
free(self);
}
* - the virtual floating point registers
* - the SSE vector register set
*/
-static int ia32_get_n_reg_class(const void *self) {
- return 3;
+static unsigned ia32_get_n_reg_class(const void *self) {
+ (void) self;
+ return N_CLASSES;
}
/**
* Return the register class for index i.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
- switch (i) {
- case 0:
- return &ia32_reg_classes[CLASS_ia32_gp];
- case 1:
- return &ia32_reg_classes[CLASS_ia32_xmm];
- case 2:
- return &ia32_reg_classes[CLASS_ia32_vfp];
- default:
- assert(0 && "Invalid ia32 register class requested.");
- return NULL;
- }
+static const arch_register_class_t *ia32_get_reg_class(const void *self,
+ unsigned i)
+{
+ (void) self;
+ assert(i < N_CLASSES);
+ return &ia32_reg_classes[i];
}
/**
const ia32_isa_t *isa = self;
ir_type *tp;
ir_mode *mode;
- unsigned cc = get_method_calling_convention(method_type);
- int n = get_method_n_params(method_type);
- int biggest_n = -1;
- int stack_idx = 0;
- int i, ignore_1, ignore_2;
- ir_mode **modes;
- const arch_register_t *reg;
+ unsigned cc;
+ int n, i, regnum;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
- unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
-
/* set abi flags for calls */
call_flags.bits.left_to_right = 0; /* always last arg first on stack */
- call_flags.bits.store_args_sequential = use_push;
+ call_flags.bits.store_args_sequential = 0;
/* call_flags.bits.try_omit_fp not changed: can handle both settings */
call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
- /* set stack parameter passing style */
+ /* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
- /* collect the mode for each type */
- modes = alloca(n * sizeof(modes[0]));
+ if (get_method_variadicity(method_type) == variadicity_variadic) {
+ /* pass all parameters of a variadic function on the stack */
+ cc = cc_cdecl_set;
+ } else {
+ cc = get_method_calling_convention(method_type);
+ if (get_method_additional_properties(method_type) & mtp_property_private
+ && (ia32_isa_template.opt & IA32_OPT_CC)) {
+ /* set the calling conventions to register parameter */
+ cc = (cc & ~cc_bits) | cc_reg_param;
+ }
+ }
- for (i = 0; i < n; i++) {
- tp = get_method_param_type(method_type, i);
- modes[i] = get_type_mode(tp);
+ /* we have to pop the shadow parameter ourself for compound calls */
+ if( (get_method_calling_convention(method_type) & cc_compound_ret)
+ && !(cc & cc_reg_param)) {
+ be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
}
- /* set register parameters */
- if (cc & cc_reg_param) {
- /* determine the number of parameters passed via registers */
- biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
+ n = get_method_n_params(method_type);
+ for (i = regnum = 0; i < n; i++) {
+ ir_mode *mode;
+ const arch_register_t *reg = NULL;
- /* loop over all parameters and set the register requirements */
- for (i = 0; i <= biggest_n; i++) {
- reg = ia32_get_RegParam_reg(n, modes, i, cc);
- assert(reg && "kaputt");
+ tp = get_method_param_type(method_type, i);
+ mode = get_type_mode(tp);
+ if (mode != NULL) {
+ reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
+ }
+ if (reg != NULL) {
be_abi_call_param_reg(abi, i, reg);
+ ++regnum;
+ } else {
+ /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
+ * movl has a shorter opcode than mov[sz][bw]l */
+ ir_mode *load_mode = mode;
+ if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
+ be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
}
-
- stack_idx = i;
}
-
- /* set stack parameters */
- for (i = stack_idx; i < n; i++) {
- /* parameters on the stack are 32 bit aligned */
- be_abi_call_param_stack(abi, i, 4, 0, 0);
- }
-
-
/* set return registers */
n = get_method_n_ress(method_type);
}
-static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
+static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
+ const ir_node *irn)
+{
+ (void) self;
+ (void) irn;
return &ia32_irn_ops;
}
ia32_get_irn_ops
};
-const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
+const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
+{
+ (void) self;
return &ia32_irn_handler;
}
-int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ia32_irn(irn) ? 1 : -1;
+int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
+{
+ (void) block_env;
+
+ if(!is_ia32_irn(irn)) {
+ return -1;
+ }
+
+ if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
+ || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
+ || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
+ || is_ia32_Immediate(irn))
+ return 0;
+
+ return 1;
}
/**
* Initializes the code generator interface.
*/
-static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
+static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
+{
+ (void) self;
return &ia32_code_gen_if;
}
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+static const list_sched_selector_t *ia32_get_list_sched_selector(
+ const void *self, list_sched_selector_t *selector)
+{
+ (void) self;
memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
ia32_sched_selector.exectime = ia32_sched_exectime;
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
-static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
+static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
+{
+ (void) self;
return NULL;
}
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
-static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
+static int ia32_get_reg_class_alignment(const void *self,
+ const arch_register_class_t *cls)
+{
ir_mode *mode = arch_register_class_mode(cls);
int bytes = get_mode_size_bytes(mode);
+ (void) self;
if (mode_is_float(mode) && bytes > 8)
return 16;
return bytes;
}
-static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
+static const be_execution_unit_t ***ia32_get_allowed_execution_units(
+ const void *self, const ir_node *irn)
+{
static const be_execution_unit_t *_allowed_units_BRANCH[] = {
&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
NULL
};
const be_execution_unit_t ***ret;
+ (void) self;
if (is_ia32_irn(irn)) {
ret = get_ia32_exec_units(irn);
/**
* Return irp irgs in the desired order.
*/
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
+static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
+{
+ (void) self;
+ (void) irg_list;
return NULL;
}
*/
static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
{
- ir_node *cmp, *cmp_a, *phi;
- ir_mode *mode;
-
-/* we don't want long long an floating point Psi */
-#define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
-
- if (get_irn_mode(sel) != mode_b)
- return 0;
-
- cmp = get_Proj_pred(sel);
- cmp_a = get_Cmp_left(cmp);
- mode = get_irn_mode(cmp_a);
-
- if (IS_BAD_PSI_MODE(mode))
- return 0;
+ ir_node *phi;
+
+ (void)sel;
+ (void)i;
+ (void)j;
+
+ /* we can't handle psis with 64bit compares yet */
+ if(is_Proj(sel)) {
+ ir_node *pred = get_Proj_pred(sel);
+ if(is_Cmp(pred)) {
+ ir_node *left = get_Cmp_left(pred);
+ ir_mode *cmp_mode = get_irn_mode(left);
+ if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
+ return 0;
+ }
+ }
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
- ir_node *pred_i = get_irn_n(phi, i);
- ir_node *pred_j = get_irn_n(phi, j);
- ir_mode *mode_i = get_irn_mode(pred_i);
- ir_mode *mode_j = get_irn_mode(pred_j);
+ ir_mode *mode = get_irn_mode(phi);
- if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
+ if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
return 0;
}
-#undef IS_BAD_PSI_MODE
-
return 1;
}
-static ia32_intrinsic_env_t intrinsic_env = {
- NULL, /**< the irg, these entities belong to */
- NULL, /**< entity for first div operand (move into FPU) */
- NULL, /**< entity for second div operand (move into FPU) */
- NULL, /**< entity for converts ll -> d */
- NULL, /**< entity for converts d -> ll */
+typedef struct insn_const {
+ int add_cost; /**< cost of an add instruction */
+ int lea_cost; /**< cost of a lea instruction */
+ int const_shf_cost; /**< cost of a constant shift instruction */
+ int cost_mul_start; /**< starting cost of a multiply instruction */
+ int cost_mul_bit; /**< cost of multiply for every set bit */
+} insn_const;
+
+/* costs for the i386 */
+static const insn_const i386_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 6, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
};
+/* costs for the i486 */
+static const insn_const i486_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 12, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium */
+static const insn_const pentium_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 11, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium Pro */
+static const insn_const pentiumpro_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the K6 */
+static const insn_const k6_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 3, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Athlon */
+static const insn_const athlon_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 5, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium 4 */
+static const insn_const pentium4_cost = {
+ 1, /* cost of an add instruction */
+ 3, /* cost of a lea instruction */
+ 4, /* cost of a constant shift instruction */
+ 15, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Core */
+static const insn_const core_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 10, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the generic */
+static const insn_const generic_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+static const insn_const *arch_costs = &generic_cost;
+
+static void set_arch_costs(enum cpu_support arch) {
+ switch (arch) {
+ case arch_i386:
+ arch_costs = &i386_cost;
+ break;
+ case arch_i486:
+ arch_costs = &i486_cost;
+ break;
+ case arch_pentium:
+ case arch_pentium_mmx:
+ arch_costs = &pentium_cost;
+ break;
+ case arch_pentium_pro:
+ case arch_pentium_2:
+ case arch_pentium_3:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_pentium_4:
+ arch_costs = &pentium4_cost;
+ break;
+ case arch_pentium_m:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_core:
+ arch_costs = &core_cost;
+ break;
+ case arch_k6:
+ arch_costs = &k6_cost;
+ break;
+ case arch_athlon:
+ case arch_athlon_xp:
+ case arch_athlon_64:
+ case arch_opteron:
+ arch_costs = &athlon_cost;
+ break;
+ case arch_generic:
+ default:
+ arch_costs = &generic_cost;
+ }
+}
+
+/**
+ * Evaluate a given simple instruction.
+ */
+static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
+ int cost;
+
+ switch (kind) {
+ case MUL:
+ cost = arch_costs->cost_mul_start;
+ if (arch_costs->cost_mul_bit > 0) {
+ char *bitstr = get_tarval_bitpattern(tv);
+ int i;
+
+ for (i = 0; bitstr[i] != '\0'; ++i) {
+ if (bitstr[i] == '1') {
+ cost += arch_costs->cost_mul_bit;
+ }
+ }
+ free(bitstr);
+ }
+ return cost;
+ case LEA:
+ return arch_costs->lea_cost;
+ case ADD:
+ case SUB:
+ return arch_costs->add_cost;
+ case SHIFT:
+ return arch_costs->const_shf_cost;
+ case ZERO:
+ return arch_costs->add_cost;
+ default:
+ return 1;
+ }
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *ia32_get_libfirm_params(void) {
- static const opt_if_conv_info_t ifconv = {
+ static const ir_settings_if_conv_t ifconv = {
4, /* maxdepth, doesn't matter for Psi-conversion */
ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
};
- static const arch_dep_params_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 31, /* maximum shift amount */
+ static const ir_settings_arch_dep_t ad = {
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 31, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* allow Mulus */
32 /* Mulh allowed up to 32 bit */
};
static backend_params p = {
+ 1, /* need dword lowering */
+ 1, /* support inline assembly */
NULL, /* no additional opcodes */
NULL, /* will be set later */
- 1, /* need dword lowering */
ia32_create_intrinsic_fkt,
&intrinsic_env, /* context for ia32_create_intrinsic_fkt */
- NULL, /* will be set later */
+ NULL, /* will be set below */
};
p.dep_param = &ad;
{ "core", arch_core, },
{ "k6", arch_k6, },
{ "athlon", arch_athlon, },
+ { "athlon-xp", arch_athlon_xp, },
{ "athlon64", arch_athlon_64, },
{ "opteron", arch_opteron, },
+ { "generic", arch_generic, },
{ NULL, 0 }
};
LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
- LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
- LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
- LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
- LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
- LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
+ LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
- { NULL }
+ LC_OPT_LAST
};
const arch_isa_if_t ia32_isa_if = {
ia32_get_irg_list,
};
+void ia32_init_emitter(void);
+void ia32_init_finish(void);
+void ia32_init_optimize(void);
+void ia32_init_transform(void);
+void ia32_init_x87(void);
+
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
+
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
+
+ ia32_init_emitter();
+ ia32_init_finish();
+ ia32_init_optimize();
+ ia32_init_transform();
+ ia32_init_x87();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
projects / libfirm / blobdiff