#include "ia32_emitter.h"
#include "ia32_map_regs.h"
#include "ia32_optimize.h"
+#include "ia32_x87.h"
#define DEBUG_MODULE "firm.be.ia32.isa"
#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
- return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
+ return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
}
ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
- return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
+ return be_abi_get_callee_save_irn(cg->birg->abi,
+ USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
}
/**************************************************
* will be asked for this information.
*/
static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
+ const ia32_irn_ops_t *ops = self;
const ia32_register_req_t *irn_req;
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
+ FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
if (is_Block(irn) || mode == mode_M || mode == mode_X) {
DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
if (is_Proj(irn)) {
if (pos == -1) {
node_pos = ia32_translate_proj_pos(irn);
/* treat Phi like Const with default requirements */
if (is_Phi(irn)) {
DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
- if (mode_is_float(mode))
- memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
+ if (mode_is_float(mode)) {
+ if (USE_SSE2(ops->cg))
+ memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
+ else
+ memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
+ }
else if (mode_is_int(mode) || mode_is_reference(mode))
memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
else if (mode == mode_T || mode == mode_M) {
ir_node *bl = get_irg_start_block(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
+ ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *store_bp;
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along);
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
set_ia32_am_support(store_bp, ia32_am_Dest);
set_ia32_am_flavour(store_bp, ia32_B);
ia32_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
+ ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
if(env->flags.try_omit_fp) {
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
}
else {
ia32_code_gen_t *cg = self;
firm_dbg_module_t *old_mod = cg->mod;
- cg->mod = firm_dbg_register("firm.be.ia32.transform");
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
const arch_register_t *out_reg, *in_reg;
int n_res, i;
ir_node *copy, *in_node, *block;
+ ia32_op_type_t op_tp;
if (! is_ia32_irn(irn))
return;
- /* nodes with destination address mode don't produce values */
- if (get_ia32_op_type(irn) == ia32_AddrModeD)
+ /* AM Dest nodes don't produce any values */
+ op_tp = get_ia32_op_type(irn);
+ if (op_tp == ia32_AddrModeD)
return;
reqs = get_ia32_out_req_all(irn);
block = get_nodes_block(irn);
/* check all OUT requirements, if there is a should_be_same */
- for (i = 0; i < n_res; i++) {
- if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
- /* get in and out register */
- out_reg = get_ia32_out_reg(irn, i);
- in_node = get_irn_n(irn, reqs[i]->same_pos);
- in_reg = arch_get_irn_register(cg->arch_env, in_node);
-
- /* check if in and out register are equal */
- if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
- DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
-
- /* create copy from in register */
- copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
- /* destination is the out register */
- arch_set_irn_register(cg->arch_env, copy, out_reg);
-
- /* insert copy before the node into the schedule */
- sched_add_before(irn, copy);
-
- /* set copy as in */
- set_irn_n(irn, reqs[i]->same_pos, copy);
+ if (op_tp == ia32_Normal) {
+ for (i = 0; i < n_res; i++) {
+ if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
+ /* get in and out register */
+ out_reg = get_ia32_out_reg(irn, i);
+ in_node = get_irn_n(irn, reqs[i]->same_pos);
+ in_reg = arch_get_irn_register(cg->arch_env, in_node);
+
+ /* don't copy ignore nodes */
+ if (arch_irn_is(cg->arch_env, in_node, ignore))
+ continue;
+
+ /* check if in and out register are equal */
+ if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
+ DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
+
+ /* create copy from in register */
+ copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
+
+ /* destination is the out register */
+ arch_set_irn_register(cg->arch_env, copy, out_reg);
+
+ /* insert copy before the node into the schedule */
+ sched_add_before(irn, copy);
+
+ /* set copy as in */
+ set_irn_n(irn, reqs[i]->same_pos, copy);
+ }
}
}
}
+ /* If we have a CondJmp with immediate, we need to */
+ /* check if it's the right operand, otherwise we have */
+ /* to change it, as CMP doesn't support immediate as */
+ /* left operands. */
+ if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
+ long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
+ set_ia32_op_type(irn, ia32_AddrModeD);
+ set_ia32_pncode(irn, pnc);
+ }
+
/* check if there is a sub which need to be transformed */
ia32_transform_sub_to_neg_add(irn, cg);
static void ia32_before_sched(void *self) {
}
+/**
+ * Called before the register allocator.
+ * Calculate a block schedule here. We need it for the x87
+ * simulator and the emitter.
+ */
static void ia32_before_ra(void *self) {
-}
+ ia32_code_gen_t *cg = self;
+ cg->blk_sched = sched_create_block_schedule(cg->irg);
+}
/**
reg = arch_get_irn_register(env->cg->arch_env, irn);
arch_set_irn_register(env->cg->arch_env, new_op, reg);
- exchange(irn, proj);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
+ exchange(irn, proj);
}
/**
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_op_type(new_op, ia32_AddrModeD);
set_ia32_am_flavour(new_op, ia32_B);
- set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_ls_mode(new_op, mode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
sched_remove(irn);
}
- exchange(irn, proj);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
+ exchange(irn, proj);
}
/**
transform_to_Load(&tenv);
}
else if (be_is_Spill(node)) {
+ /* we always spill the whole register */
+ tenv.mode = mode_is_float(get_irn_mode(be_get_Spill_context(node))) ? mode_D : mode_Is;
transform_to_Store(&tenv);
}
}
static void ia32_after_ra(void *self) {
ia32_code_gen_t *cg = self;
irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
+
+ /* if we do x87 code generation, rewrite all the virtual instructions and registers */
+ if (cg->used_x87) {
+ x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
+ be_dump(cg->irg, "-x87", dump_ir_extblock_graph_sched);
+ }
}
ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
- cg->impl = &ia32_code_gen_if;
- cg->irg = birg->irg;
- cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("firm.be.ia32.cg");
- cg->out = F;
- cg->arch_env = birg->main_env->arch_env;
- cg->types = pmap_create();
- cg->tv_ent = pmap_create();
- cg->birg = birg;
+ cg->impl = &ia32_code_gen_if;
+ cg->irg = birg->irg;
+ cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
+ cg->out = F;
+ cg->arch_env = birg->main_env->arch_env;
+ cg->types = pmap_create();
+ cg->tv_ent = pmap_create();
+ cg->birg = birg;
+ cg->blk_sched = NULL;
+ cg->fp_kind = isa->fp_kind;
+ cg->used_x87 = 0;
+
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
/* set optimizations */
cg->opt.incdec = 0;
0, /* number of code generator objects so far */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
+ fp_sse2, /* use SSE2 unit for fp operations */
#ifndef NDEBUG
NULL, /* name obstack */
0 /* name obst size */
ia32_register_init(isa);
ia32_create_opcodes();
+ ia32_register_copy_attr_func();
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
+// isa->fp_kind = fp_x87;
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
}
-
+/**
+ * Return the number of register classes for this architecture.
+ * We report always these:
+ * - the general purpose registers
+ * - the floating point register set (depending on the unit used for FP)
+ * - MMX/SE registers (currently not supported)
+ */
static int ia32_get_n_reg_class(const void *self) {
- return N_CLASSES;
+ return 2;
}
+/**
+ * Return the register class for index i.
+ */
static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
- return &ia32_reg_classes[i];
+ const ia32_isa_t *isa = self;
+ assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
+ if (i == 0)
+ return &ia32_reg_classes[CLASS_ia32_gp];
+ return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
}
/**
* @return A register class which can hold values of the given mode.
*/
const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
- if (mode_is_float(mode))
- return &ia32_reg_classes[CLASS_ia32_fp];
+ const ia32_isa_t *isa = self;
+ if (mode_is_float(mode)) {
+ return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
+ }
else
return &ia32_reg_classes[CLASS_ia32_gp];
}
* @param method_type The type of the method (procedure) in question.
* @param abi The abi object to be modified
*/
-void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+ const ia32_isa_t *isa = self;
ir_type *tp;
ir_mode *mode;
unsigned cc = get_method_calling_convention(method_type);
/* set stack parameters */
for (i = stack_idx; i < n; i++) {
- be_abi_call_param_stack(abi, i, 1);
+ be_abi_call_param_stack(abi, i, 1, 0, 0);
}
be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
}
else if (n == 1) {
+ const arch_register_t *reg;
+
tp = get_method_res_type(method_type, 0);
assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
+ reg = mode_is_float(mode) ?
+ (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
+ &ia32_gp_regs[REG_EAX];
+
+ be_abi_call_res_reg(abi, 0, reg);
}
}