if (! is_ia32_irn(irn))
return classification & ~arch_irn_class_normal;
- if (is_ia32_Cnst(irn))
- classification |= arch_irn_class_const;
-
if (is_ia32_Ld(irn))
classification |= arch_irn_class_load;
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
- ia32_am_flavour_t am_flav;
-
if (is_ia32_Pop(irn)) {
int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
if (omit_fp) {
}
}
- am_flav = get_ia32_am_flavour(irn);
- am_flav |= ia32_O;
- set_ia32_am_flavour(irn, am_flav);
-
add_ia32_am_offs_int(irn, bias);
}
}
cost += 150;
}
else if (is_ia32_CopyB_i(irn)) {
- int size = get_tarval_long(get_ia32_Immop_tarval(irn));
+ int size = get_ia32_pncode(irn);
cost = 20 + (int)ceil((4/3) * size);
if (ARCH_INTEL(ops->cg->arch))
cost += 150;
if (get_ia32_op_type(irn) != ia32_Normal)
return NULL;
+ /* TODO: adjust for new immediates... */
+ ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
+ irn);
+ return NULL;
+
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
+#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
inverse->costs += 2;
}
+#endif
break;
case iro_ia32_Sub:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
}
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Xor:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
}
set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
if (mode_is_float(spillmode)) {
if (USE_SSE2(cg))
- new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
}
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
}
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
- set_ia32_am_flavour(push, ia32_B);
set_ia32_ls_mode(push, mode_Is);
sched_add_before(schedpoint, push);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
- set_ia32_am_flavour(pop, ia32_am_OB);
set_ia32_ls_mode(pop, mode_Is);
sched_add_before(schedpoint, pop);
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) {
if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = get_mode_size_bytes(mode);
+ const ir_mode *mode = get_ia32_ls_mode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int align = get_mode_size_bytes(mode);
+
+ if(attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ }
+ if(attr->data.need_32bit_stackent) {
+ mode = mode_Is;
+ }
be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
|| is_ia32_vfld(node)) {
* Set output modes for GCC
*/
static const tarval_mode_info mo_integer = {
- TVO_DECIMAL,
- NULL,
+ TVO_HEX,
+ "0x",
NULL,
};
#endif
};
+static void set_arch_costs(enum cpu_support arch);
+
/**
* Initializes the backend ISA.
*/
ia32_register_init();
ia32_create_opcodes();
+ set_arch_costs(isa->opt_arch);
+
if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
(ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
/* no SSE2 for these cpu's */
(void)i;
(void)j;
+#if 1
if(is_Proj(sel)) {
ir_node *pred = get_Proj_pred(sel);
if(is_Cmp(pred)) {
return 0;
}
}
+#endif
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
return 1;
}
+typedef struct insn_const {
+ int add_cost; /**< cost of an add instruction */
+ int lea_cost; /**< cost of a lea instruction */
+ int const_shf_cost; /**< cost of a constant shift instruction */
+ int cost_mul_start; /**< starting cost of a multiply instruction */
+ int cost_mul_bit; /**< cost of multiply for every set bit */
+} insn_const;
+
+/* costs for the i386 */
+static const insn_const i386_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 6, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
+};
+
+/* costs for the i486 */
+static const insn_const i486_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 12, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium */
+static const insn_const pentium_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 11, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium Pro */
+static const insn_const pentiumpro_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the K6 */
+static const insn_const k6_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 3, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Athlon */
+static const insn_const athlon_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 5, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium 4 */
+static const insn_const pentium4_cost = {
+ 1, /* cost of an add instruction */
+ 3, /* cost of a lea instruction */
+ 4, /* cost of a constant shift instruction */
+ 15, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Core */
+static const insn_const core_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 10, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the generic */
+static const insn_const generic_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+static const insn_const *arch_costs = &generic_cost;
+
+static void set_arch_costs(enum cpu_support arch) {
+ switch (arch) {
+ case arch_i386:
+ arch_costs = &i386_cost;
+ break;
+ case arch_i486:
+ arch_costs = &i486_cost;
+ break;
+ case arch_pentium:
+ case arch_pentium_mmx:
+ arch_costs = &pentium_cost;
+ break;
+ case arch_pentium_pro:
+ case arch_pentium_2:
+ case arch_pentium_3:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_pentium_4:
+ arch_costs = &pentium4_cost;
+ break;
+ case arch_pentium_m:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_core:
+ arch_costs = &core_cost;
+ break;
+ case arch_k6:
+ arch_costs = &k6_cost;
+ break;
+ case arch_athlon:
+ case arch_athlon_64:
+ case arch_opteron:
+ arch_costs = &athlon_cost;
+ break;
+ case arch_generic:
+ default:
+ arch_costs = &generic_cost;
+ }
+}
+
+/**
+ * Evaluate a given simple instruction.
+ */
+static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
+ int cost;
+
+ switch (kind) {
+ case MUL:
+ cost = arch_costs->cost_mul_start;
+ if (arch_costs->cost_mul_bit > 0) {
+ char *bitstr = get_tarval_bitpattern(tv);
+ int i;
+
+ for (i = 0; bitstr[i] != '\0'; ++i) {
+ if (bitstr[i] == '1') {
+ cost += arch_costs->cost_mul_bit;
+ }
+ }
+ free(bitstr);
+ }
+ return cost;
+ case LEA:
+ return arch_costs->lea_cost;
+ case ADD:
+ case SUB:
+ return arch_costs->add_cost;
+ case SHIFT:
+ return arch_costs->const_shf_cost;
+ case ZERO:
+ return arch_costs->add_cost;
+ default:
+ return 1;
+ }
+}
+
static ia32_intrinsic_env_t intrinsic_env = {
NULL, /**< the irg, these entities belong to */
NULL, /**< entity for first div operand (move into FPU) */
NULL, /**< entity for second div operand (move into FPU) */
NULL, /**< entity for converts ll -> d */
NULL, /**< entity for converts d -> ll */
+ NULL, /**< entity for __divdi3 library call */
+ NULL, /**< entity for __moddi3 library call */
+ NULL, /**< entity for __udivdi3 library call */
+ NULL, /**< entity for __umoddi3 library call */
};
/**
ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
};
static const ir_settings_arch_dep_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 31, /* maximum shift amount */
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 31, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* allow Mulus */
{ "athlon", arch_athlon, },
{ "athlon64", arch_athlon_64, },
{ "opteron", arch_opteron, },
+ { "generic", arch_generic, },
{ NULL, 0 }
};
projects / libfirm / blobdiff