+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irprog.h"
#include "irprintf.h"
-#include "bearch_ia32.h"
+#include "iredges_t.h"
#include "bitset.h"
#include "debug.h"
-#include <obstack.h>
-
-#ifdef obstack_chunk_alloc
-# undef obstack_chunk_alloc
-# define obstack_chunk_alloc malloc
-#else
-# define obstack_chunk_alloc malloc
-# define obstack_chunk_free free
-#endif
-
#include "../bearch.h" /* the general register allocator interface */
+#include "../benode_t.h"
+#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
return (ir_node *)n;
}
+static int is_Call_Proj(const ir_node *n) {
+ if (is_Proj(n) &&
+ is_Proj(get_Proj_pred(n)) &&
+ get_irn_mode(get_Proj_pred(n)) == mode_T &&
+ is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
+ {
+ return 1;
+ }
+
+ return 0;
+}
+
+static int is_P_frame_base_Proj(const ir_node *n) {
+ if (is_Proj(n) &&
+ get_irn_opcode(get_Proj_pred(n)) == iro_Start &&
+ get_Proj_proj(n) == pn_Start_P_frame_base)
+ {
+ return 1;
+ }
+
+ return 0;
+}
+
+static int is_used_by_Keep(const ir_node *n) {
+ return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
+}
+
/**
* Return register requirements for an ia32 node.
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
static const arch_register_req_t *ia32_get_irn_reg_req(const arch_irn_ops_t *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const arch_register_req_t *irn_req;
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = get_irn_mode(irn);
- firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
+ const ia32_register_req_t *irn_req;
+ long node_pos = pos == -1 ? 0 : pos;
+ ir_mode *mode = get_irn_mode(irn);
+ firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
if (mode == mode_T || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
- if (is_Proj(irn)) {
- if (pos == -1)
- node_pos = translate_proj_pos(irn);
- else
+
+ if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
+ irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
+ memcpy(req, &(irn_req->req), sizeof(*req));
+ return req;
+ }
+ else if (is_Proj(irn)) {
+ if (pos == -1) {
+ node_pos = ia32_translate_proj_pos(irn);
+ }
+ else {
node_pos = pos;
+ }
irn = my_skip_proj(irn);
DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
- memcpy(req, irn_req, sizeof(*req));
- return req;
+ memcpy(req, &(irn_req->req), sizeof(*req));
+
+ if (arch_register_req_is(&(irn_req->req), should_be_same) ||
+ arch_register_req_is(&(irn_req->req), should_be_different)) {
+ assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
+ req->other = get_irn_n(irn, irn_req->pos);
+ }
}
else {
/* treat Phi like Const with default requirements */
if (is_Phi(irn)) {
DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
if (mode_is_float(mode))
- memcpy(req, &ia32_default_req_ia32_floating_point, sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
else if (mode_is_int(mode) || mode_is_reference(mode))
- memcpy(req, &ia32_default_req_ia32_general_purpose, sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_general_purpose.req), sizeof(*req));
else if (mode == mode_T || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
return NULL;
case pn_Start_X_initial_exec:
case pn_Start_P_value_arg_base:
case pn_Start_P_globals:
- memcpy(req, &ia32_default_req_none, sizeof(*req));
- break;
case pn_Start_P_frame_base:
- memcpy(req, &ia32_default_req_none, sizeof(*req));
+ memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
break;
case pn_Start_T_args:
assert(0 && "ProjT(pn_Start_T_args) should not be asked");
}
else if (get_irn_op(irn) == op_Return && pos > 0) {
DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
- memcpy(req, &ia32_default_req_ia32_general_purpose_eax, sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
}
else {
DBG((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
static void ia32_set_irn_reg(const arch_irn_ops_t *self, ir_node *irn, const arch_register_t *reg) {
int pos = 0;
- if (is_Proj(irn)) {
- pos = translate_proj_pos(irn);
+ if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) || is_P_frame_base_Proj(irn)) {
+ /* don't skip the proj, we want to take the else below */
+ }
+ else if (is_Proj(irn)) {
+ pos = ia32_translate_proj_pos(irn);
irn = my_skip_proj(irn);
}
slots[pos] = reg;
}
else {
- ia32_set_firm_reg(self, irn, reg, cur_reg_set);
+ ia32_set_firm_reg(irn, reg, cur_reg_set);
}
}
int pos = 0;
const arch_register_t *reg = NULL;
- if (is_Proj(irn)) {
- pos = translate_proj_pos(irn);
+ if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) || is_P_frame_base_Proj(irn)) {
+ /* don't skip the proj, we want to take the else below */
+ }
+ else if (is_Proj(irn)) {
+ pos = ia32_translate_proj_pos(irn);
irn = my_skip_proj(irn);
}
reg = slots[pos];
}
else {
- reg = ia32_get_firm_reg(self, irn, cur_reg_set);
+ reg = ia32_get_firm_reg(irn, cur_reg_set);
}
return reg;
irn = my_skip_proj(irn);
if (is_cfop(irn))
return arch_irn_class_branch;
+ else if (is_ia32_Call(irn))
+ return arch_irn_class_call;
else if (is_ia32_irn(irn))
return arch_irn_class_normal;
else
* |___/
**************************************************/
-typedef struct _ia32_isa_t {
- const arch_isa_if_t *impl;
- int num_codegens;
-} ia32_isa_t;
-
-typedef struct _ia32_code_gen_t {
- const arch_code_generator_if_t *impl; /* implementation */
- ir_graph *irg; /* current irg */
- FILE *out; /* output file */
- const arch_env_t *arch_env; /* the arch env */
- set *reg_set; /* set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
- firm_dbg_module_t *mod; /* debugging module */
- int emit_decls;
-} ia32_code_gen_t;
+static void check_for_alloca(ir_node *irn, void *env) {
+ int *has_alloca = env;
+
+ if (get_irn_opcode(irn) == iro_Alloc) {
+ if (get_Alloc_where(irn) == stack_alloc) {
+ *has_alloca = 1;
+ }
+ }
+}
/**
* Transforms the standard firm graph into
* an ia32 firm graph
*/
static void ia32_prepare_graph(void *self) {
- ia32_code_gen_t *cg = self;
+ ia32_code_gen_t *cg = self;
+ int has_alloca = 0;
- if (! is_pseudo_ir_graph(cg->irg))
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg->mod);
+ if (! is_pseudo_ir_graph(cg->irg)) {
+ /* If there is a alloca in the irg, we use %ebp for stack addressing */
+ /* instead of %esp, as alloca destroys %esp. */
+
+ /* check for alloca node */
+ irg_walk_blkwise_graph(cg->irg, check_for_alloca, NULL, &has_alloca);
+
+ if (has_alloca) {
+ ia32_general_purpose_regs[REG_EBP].type = arch_register_type_ignore;
+ }
+
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
+ }
}
/**
- * Dummy functions for hooks we don't need but which must be filled.
+ * Set the register for P_frame_base Proj to %esp.
*/
-static void ia32_before_sched(void *self) {
+static void ia32_set_P_frame_base_Proj_reg(ir_node *irn, void *env) {
+ ia32_code_gen_t *cg = env;
+
+ if (is_P_frame_base_Proj(irn)) {
+ arch_set_irn_register(cg->arch_env, irn, &ia32_general_purpose_regs[REG_ESP]);
+ }
}
+/**
+ * This function is the hook before_sched but more important: it is
+ * called after the dead node elimination. The dead node elimination changes
+ * the memory location of the nodes, which will change the hash key of
+ * the Proj_P_frame_base(Start) and this will fuck up the firm_node -> register
+ * hash map. So we need to insert the register for this node after the dead node
+ * elimination.
+ */
+static void ia32_some_stuff_need_to_be_done_after_deadnode_elimination(void *self) {
+ ia32_code_gen_t *cg = self;
+
+ if (! is_pseudo_ir_graph(cg->irg))
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_set_P_frame_base_Proj_reg, cg);
+}
+
+
+
+/**
+ * Dummy functions for hooks we don't need but which must be filled.
+ */
static void ia32_before_ra(void *self) {
}
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
ia32_prepare_graph,
- ia32_before_sched, /* before scheduling hook */
+ ia32_some_stuff_need_to_be_done_after_deadnode_elimination, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
ia32_codegen /* emit && done */
};
cg->impl = &ia32_code_gen_if;
cg->irg = irg;
- cg->reg_set = new_set(cmp_irn_reg_assoc, 1024);
+ cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
cg->mod = firm_dbg_register("be.transform.ia32");
cg->out = F;
cg->arch_env = arch_env;
inited = 1;
- isa->num_codegens = 0;
+ isa->num_codegens = 0;
+ isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
- ia32_register_init();
+ ia32_register_init(isa);
ia32_create_opcodes();
return isa;
return &ia32_irn_handler;
}
+long ia32_get_call_projnum_for_reg(const void *self, const arch_register_t *reg) {
+ ia32_isa_t *isa = (ia32_isa_t *)self;
+ return ia32_get_reg_projnum(reg, isa->reg_projnum_map);
+}
+int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
+ return is_ia32_irn(irn);
+}
/**
* Initializes the code generator interface.
return &ia32_code_gen_if;
}
+list_sched_selector_t ia32_sched_selector;
+
/**
- * Returns the default scheduler
+ * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
- return trivial_selector;
+ memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
+ ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
+ return &ia32_sched_selector;
}
#ifdef WITH_LIBCORE
ia32_get_reg_class,
ia32_get_irn_handler,
ia32_get_code_generator_if,
- ia32_get_list_sched_selector
+ ia32_get_list_sched_selector,
+ ia32_get_call_projnum_for_reg
};
projects / libfirm / blobdiff