#include "iroptimize.h"
#include "instrument.h"
#include "iropt_t.h"
+#include "lower_dw.h"
#include "../beabi.h"
#include "../beirg.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_emitter.h"
-#include "ia32_map_regs.h"
#include "ia32_optimize.h"
#include "ia32_x87.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
-#include "ia32_util.h"
#include "ia32_fpu.h"
#include "ia32_architecture.h"
transformer_t be_transformer = TRANSFORMER_DEFAULT;
#endif
-DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-
-ir_mode *mode_fpcw = NULL;
+ir_mode *ia32_mode_fpcw = NULL;
/** The current omit-fp state */
-static unsigned ia32_curr_fp_ommitted = 0;
static ir_type *omit_fp_between_type = NULL;
static ir_type *between_type = NULL;
static ir_entity *old_bp_ent = NULL;
};
-typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
+typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
/**
* Used to create per-graph unique pseudo nodes.
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
- &ia32_gp_regs[REG_GP_NOREG]);
+ &ia32_registers[REG_GP_NOREG]);
}
ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
- &ia32_vfp_regs[REG_VFP_NOREG]);
+ &ia32_registers[REG_VFP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
- &ia32_xmm_regs[REG_XMM_NOREG]);
+ &ia32_registers[REG_XMM_NOREG]);
}
ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
- &ia32_fp_cw_regs[REG_FPCW]);
+ &ia32_registers[REG_FPCW]);
}
static arch_irn_class_t ia32_classify(const ir_node *irn)
{
- arch_irn_class_t classification = 0;
+ arch_irn_class_t classification = arch_irn_class_none;
assert(is_ia32_irn(irn));
if (is_ia32_Pop(node) || is_ia32_PopMem(node))
return -4;
- return 0;
-}
-
-/**
- * Generate the routine prologue.
- *
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @param stack_bias Points to the current stack bias, can be modified if needed.
- *
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
-{
- ia32_abi_env_t *env = self;
- ir_graph *irg = env->irg;
- const arch_env_t *arch_env = be_get_irg_arch_env(irg);
-
- ia32_curr_fp_ommitted = env->flags.try_omit_fp;
- if (! env->flags.try_omit_fp) {
- ir_node *bl = get_irg_start_block(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
- ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *push;
-
- /* mark bp register as ignore */
- be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
- get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
-
- /* push ebp */
- push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
- curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
- *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
-
- /* the push must have SP out register */
- arch_set_irn_register(curr_sp, arch_env->sp);
-
- /* this modifies the stack bias, because we pushed 32bit */
- *stack_bias -= 4;
-
- /* move esp to ebp */
- curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
- be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
- arch_register_req_type_ignore);
-
- /* beware: the copy must be done before any other sp use */
- curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
- be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
- arch_register_req_type_produces_sp);
-
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-
- return arch_env->bp;
- }
-
- return arch_env->sp;
-}
-
-/**
- * Generate the routine epilogue.
- * @param self The callback object.
- * @param bl The block for the epilog
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
-{
- ia32_abi_env_t *env = self;
- const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
-
- if (env->flags.try_omit_fp) {
- /* simply remove the stack frame here */
- curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
- } else {
- ir_mode *mode_bp = arch_env->bp->reg_class->mode;
-
- if (ia32_cg_config.use_leave) {
- ir_node *leave;
-
- /* leave */
- leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
- curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
- curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
- } else {
- ir_node *pop;
-
- /* the old SP is not needed anymore (kill the proj) */
- assert(is_Proj(curr_sp));
- kill_node(curr_sp);
-
- /* copy ebp to esp */
- curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
- arch_set_irn_register(curr_sp, arch_env->sp);
- be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
- arch_register_req_type_ignore);
-
- /* pop ebp */
- pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
- curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
- curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
-
- *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
- }
- arch_set_irn_register(curr_sp, arch_env->sp);
- arch_set_irn_register(curr_bp, arch_env->bp);
+ if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
+ return SP_BIAS_RESET;
}
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-}
-
-/**
- * Initialize the callback object.
- * @param call The call object.
- * @param irg The graph with the method.
- * @return Some pointer. This pointer is passed to all other callback functions as self object.
- */
-static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
-{
- ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- return env;
-}
-
-/**
- * Destroy the callback object.
- * @param self The callback object.
- */
-static void ia32_abi_done(void *self)
-{
- free(self);
+ return 0;
}
/**
* it will contain the return address and space to store the old base pointer.
* @return The Firm type modeling the ABI between type.
*/
-static ir_type *ia32_abi_get_between_type(void *self)
+static ir_type *ia32_abi_get_between_type(ir_graph *irg)
{
- ia32_abi_env_t *env = self;
-
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
+ return layout->sp_relative ? omit_fp_between_type : between_type;
}
/**
* Return the stack entity that contains the return address.
*/
-ir_entity *ia32_get_return_address_entity(void)
+ir_entity *ia32_get_return_address_entity(ir_graph *irg)
{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
+ return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
}
/**
* Return the stack entity that contains the frame address.
*/
-ir_entity *ia32_get_frame_address_entity(void)
+ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
+ return layout->sp_relative ? NULL : old_bp_ent;
}
/**
cycles.
*/
if (is_ia32_use_frame(irn) || (
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
- is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+ is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
)) {
cost += 5;
} else {
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
- dbg_info *dbg;
+ dbg_info *dbgi;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
mode = get_irn_mode(irn);
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
- nomem = new_NoMem();
- dbg = get_irn_dbg_info(irn);
+ nomem = get_irg_no_mem(irg);
+ dbgi = get_irn_dbg_info(irn);
/* initialize structure */
inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
-#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
-#endif
break;
case iro_ia32_Sub:
-#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
if (i == n_ia32_binary_left) {
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
+ inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
-#endif
break;
case iro_ia32_Xor:
-#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
+ inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
-#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
+ inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
- ia32_abi_init,
- ia32_abi_done,
ia32_abi_get_between_type,
- ia32_abi_prologue,
- ia32_abi_epilogue
};
/* register allocator interface */
};
static ir_entity *mcount = NULL;
+static int gprof = 0;
static void ia32_before_abi(ir_graph *irg)
{
- if (be_get_irg_options(irg)->gprof) {
+ if (gprof) {
if (mcount == NULL) {
ir_type *tp = new_type_method(0, 0);
ident *id = new_id_from_str("mcount");
dump_ir_graph(irg, "place");
}
-ir_node *turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
{
dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
ir_node *base = get_irn_n(node, n_ia32_base);
- ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
ir_node *mem = get_irn_n(node, n_ia32_mem);
ir_node *noreg;
- ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
+ ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
if (is_ia32_is_reload(node))
set_ia32_is_reload(load);
- set_irn_n(node, n_ia32_mem, new_NoMem());
+ set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
switch (get_ia32_am_support(node)) {
case ia32_am_unary:
type = get_ia32_op_type(node);
switch (type) {
case ia32_AddrModeS:
- turn_back_am(node);
+ ia32_turn_back_am(node);
break;
case ia32_AddrModeD:
/* TODO implement this later... */
panic("found DestAM with flag user %+F this should not happen", node);
- break;
default: assert(type == ia32_Normal); break;
}
static void transform_to_Load(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(irg);
- ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_node *mem = get_irn_n(node, n_be_Reload_mem);
ir_node *new_op, *proj;
const arch_register_t *reg;
if (mode_is_float(spillmode)) {
if (ia32_cg_config.use_sse2)
- new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
- new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
}
else
- new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, spillmode);
DBG_OPT_RELOAD2LD(node, new_op);
- proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
+ proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
static void transform_to_Store(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
- const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
+ const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
ir_mode *mode = get_spill_mode(spillval);
ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *nomem = new_NoMem();
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *ptr = get_irg_frame(irg);
- ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_node *val = get_irn_n(node, n_be_Spill_val);
+ ir_node *res;
ir_node *store;
ir_node *sched_point = NULL;
}
if (mode_is_float(mode)) {
- if (ia32_cg_config.use_sse2)
- store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
- else
- store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
+ if (ia32_cg_config.use_sse2) {
+ store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
+ } else {
+ store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
+ res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ }
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
- store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
- store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
set_ia32_op_type(store, ia32_AddrModeD);
sched_remove(node);
}
- exchange(node, store);
+ exchange(node, res);
}
static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_graph *irg = get_irn_irg(node);
- ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *frame = get_irg_frame(irg);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
+ ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_irn_irg(node);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
+ ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
+ get_irg_no_mem(irg), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_mode *spmode = mode_Iu;
- const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *spmode = mode_Iu;
+ const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
- sp = new_rd_Proj(dbg, pred, spmode, pos);
+ sp = new_rd_Proj(dbgi, pred, spmode, pos);
arch_set_irn_register(sp, spreg);
return sp;
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_irn_irg(node);
- ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_gp_regs[REG_ESP]);
+ ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
int arity = be_get_MemPerm_entity_arity(node);
ir_node **pops = ALLOCAN(ir_node*, arity);
ir_node *in[1];
sp = create_spproj(node, push, pn_ia32_Push_stack);
}
- set_irn_n(node, i, new_Bad());
+ set_irn_n(node, i, new_r_Bad(irg, mode_X));
}
/* create pops */
}
/* remove memperm */
- arity = get_irn_arity(node);
- for (i = 0; i < arity; ++i) {
- set_irn_n(node, i, new_Bad());
- }
sched_remove(node);
+ kill_node(node);
}
/**
*/
static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = (be_fec_env_t*)data;
const ir_mode *mode;
int align;
be_node_needs_frame_entity(env, node, mode, align);
}
+static int determine_ebp_input(ir_node *ret)
+{
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ int arity = get_irn_arity(ret);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *input = get_irn_n(ret, i);
+ if (arch_get_irn_register(input) == bp)
+ return i;
+ }
+ panic("no ebp input found at %+F", ret);
+}
+
+static void introduce_epilog(ir_node *ret)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_graph *irg = get_irn_irg(ret);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *block = get_nodes_block(ret);
+ ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
+ ir_node *curr_sp = first_sp;
+ ir_mode *mode_gp = mode_Iu;
+
+ if (!layout->sp_relative) {
+ int n_ebp = determine_ebp_input(ret);
+ ir_node *curr_bp = get_irn_n(ret, n_ebp);
+ if (ia32_cg_config.use_leave) {
+ ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
+ curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, leave);
+ } else {
+ ir_node *pop;
+ ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
+ /* copy ebp to esp */
+ curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, curr_sp);
+
+ /* pop ebp */
+ pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
+ curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
+ curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
+ curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, pop);
+
+ set_irn_n(ret, n_be_Return_mem, curr_mem);
+ }
+ set_irn_n(ret, n_ebp, curr_bp);
+ } else {
+ ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
+ sched_add_before(ret, incsp);
+ curr_sp = incsp;
+ }
+ set_irn_n(ret, n_be_Return_sp, curr_sp);
+
+ /* keep verifier happy... */
+ if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
+ kill_node(first_sp);
+ }
+}
+
+/**
+ * put the Prolog code at the beginning, epilog code before each return
+ */
+static void introduce_prolog_epilog(ir_graph *irg)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_node *start = get_irg_start(irg);
+ ir_node *block = get_nodes_block(start);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
+ ir_node *curr_sp = initial_sp;
+ ir_mode *mode_gp = mode_Iu;
+
+ if (!layout->sp_relative) {
+ /* push ebp */
+ ir_node *mem = get_irg_initial_mem(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
+ ir_node *curr_bp = initial_bp;
+ ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
+ ir_node *incsp;
+
+ curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
+ mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_after(start, push);
+
+ /* move esp to ebp */
+ curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
+ sched_add_after(push, curr_bp);
+ be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
+ curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
+ sched_add_after(curr_bp, curr_sp);
+ be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
+ edges_reroute(initial_bp, curr_bp);
+ set_irn_n(push, n_ia32_Push_val, initial_bp);
+
+ incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
+ edges_reroute(initial_sp, incsp);
+ set_irn_n(push, n_ia32_Push_stack, initial_sp);
+ sched_add_after(curr_sp, incsp);
+
+ layout->initial_bias = -4;
+ } else {
+ ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
+ edges_reroute(initial_sp, incsp);
+ be_set_IncSP_pred(incsp, curr_sp);
+ sched_add_after(start, incsp);
+ }
+
+ /* introduce epilog for every return node */
+ {
+ ir_node *end_block = get_irg_end_block(irg);
+ int arity = get_irn_arity(end_block);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *ret = get_irn_n(end_block, i);
+ assert(be_is_Return(ret));
+ introduce_epilog(ret);
+ }
+ }
+}
+
/**
* We transform Spill and Reload here. This needs to be done before
* stack biasing otherwise we would miss the corrected offset for these nodes.
*/
static void ia32_after_ra(ir_graph *irg)
{
- be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+ be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
+ bool at_begin = stack_layout->sp_relative ? true : false;
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
/* create and coalesce frame entities */
irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
- be_assign_entities(fec_env, ia32_set_frame_entity);
+ be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
be_free_frame_entity_coalescer(fec_env);
irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
+
+ introduce_prolog_epilog(irg);
}
/**
/* we might have to rewrite x87 virtual registers */
if (irg_data->do_x87_sim) {
- x87_simulate_graph(irg);
+ ia32_x87_simulate_graph(irg);
}
/* do peephole optimisations */
get_eip = new_bd_ia32_GetEIP(NULL, block);
irg_data->get_eip = get_eip;
- be_dep_on_frame(get_eip);
return get_eip;
}
irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
- if (be_get_irg_options(irg)->gprof) {
+ if (gprof) {
/* Linux gprof implementation needs base pointer */
be_get_irg_options(irg)->omit_fp = 0;
}
*/
static void set_tarval_output_modes(void)
{
- int i;
+ size_t i;
- for (i = get_irp_n_modes() - 1; i >= 0; --i) {
- ir_mode *mode = get_irp_mode(i);
+ for (i = get_irp_n_modes(); i > 0;) {
+ ir_mode *mode = get_irp_mode(--i);
if (mode_is_int(mode))
set_tarval_mode_output_option(mode, &mo_integer);
}
}
-const arch_isa_if_t ia32_isa_if;
+extern const arch_isa_if_t ia32_isa_if;
/**
* The template that generates a new ISA object.
static ia32_isa_t ia32_isa_template = {
{
&ia32_isa_if, /* isa interface implementation */
- &ia32_gp_regs[REG_ESP], /* stack pointer register */
- &ia32_gp_regs[REG_EBP], /* base pointer register */
+ N_IA32_REGISTERS,
+ ia32_registers,
+ N_IA32_CLASSES,
+ ia32_reg_classes,
+ &ia32_registers[REG_ESP], /* stack pointer register */
+ &ia32_registers[REG_EBP], /* base pointer register */
&ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
- -1, /* stack direction */
2, /* power of two stack alignment, 2^2 == 4 */
NULL, /* main environment */
7, /* costs for a spill instruction */
5, /* costs for a reload instruction */
false, /* no custom abi handling */
},
- NULL, /* 16bit register names */
- NULL, /* 8bit register names */
- NULL, /* 8bit register names high */
NULL, /* types */
NULL, /* tv_ents */
NULL, /* abstract machine */
*/
static arch_env_t *ia32_init(FILE *file_handle)
{
- static int inited = 0;
- ia32_isa_t *isa;
- int i, n;
-
- if (inited)
- return NULL;
- inited = 1;
+ ia32_isa_t *isa = XMALLOC(ia32_isa_t);
set_tarval_output_modes();
- isa = XMALLOC(ia32_isa_t);
- memcpy(isa, &ia32_isa_template, sizeof(*isa));
+ *isa = ia32_isa_template;
- if (mode_fpcw == NULL) {
- mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ if (ia32_mode_fpcw == NULL) {
+ ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
}
ia32_register_init();
ia32_create_opcodes(&ia32_irn_ops);
be_emit_init(file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->regs_8bit_high = pmap_create();
isa->types = pmap_create();
isa->tv_ent = pmap_create();
isa->cpu = ia32_init_machine_description();
- ia32_build_16bit_reg_map(isa->regs_16bit);
- ia32_build_8bit_reg_map(isa->regs_8bit);
- ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
-
/* enter the ISA object into the intrinsic environment */
intrinsic_env.isa = isa;
- /* emit asm includes */
- n = get_irp_n_asms();
- for (i = 0; i < n; ++i) {
- be_emit_cstring("#APP\n");
- be_emit_ident(get_irp_asm(i));
- be_emit_cstring("\n#NO_APP\n");
- }
-
- /* needed for the debug support */
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
- be_emit_write_line();
-
return &isa->base;
}
*/
static void ia32_done(void *self)
{
- ia32_isa_t *isa = self;
+ ia32_isa_t *isa = (ia32_isa_t*)self;
/* emit now all global declarations */
be_gas_emit_decls(isa->base.main_env);
- pmap_destroy(isa->regs_16bit);
- pmap_destroy(isa->regs_8bit);
- pmap_destroy(isa->regs_8bit_high);
pmap_destroy(isa->tv_ent);
pmap_destroy(isa->types);
}
-/**
- * Return the number of register classes for this architecture.
- * We report always these:
- * - the general purpose registers
- * - the SSE floating point register set
- * - the virtual floating point registers
- * - the SSE vector register set
- */
-static unsigned ia32_get_n_reg_class(void)
-{
- return N_CLASSES;
-}
-
-/**
- * Return the register class for index i.
- */
-static const arch_register_class_t *ia32_get_reg_class(unsigned i)
-{
- assert(i < N_CLASSES);
- return &ia32_reg_classes[i];
-}
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
const ir_mode *mode)
{
static const arch_register_t *gpreg_param_reg_fastcall[] = {
- &ia32_gp_regs[REG_ECX],
- &ia32_gp_regs[REG_EDX],
+ &ia32_registers[REG_ECX],
+ &ia32_registers[REG_EDX],
NULL
};
static const unsigned MAXNUM_GPREG_ARGS = 3;
static const arch_register_t *gpreg_param_reg_regparam[] = {
- &ia32_gp_regs[REG_EAX],
- &ia32_gp_regs[REG_EDX],
- &ia32_gp_regs[REG_ECX]
+ &ia32_registers[REG_EAX],
+ &ia32_registers[REG_EDX],
+ &ia32_registers[REG_ECX]
};
static const arch_register_t *gpreg_param_reg_this[] = {
- &ia32_gp_regs[REG_ECX],
+ &ia32_registers[REG_ECX],
NULL,
NULL
};
static const arch_register_t *fpreg_sse_param_reg_std[] = {
- &ia32_xmm_regs[REG_XMM0],
- &ia32_xmm_regs[REG_XMM1],
- &ia32_xmm_regs[REG_XMM2],
- &ia32_xmm_regs[REG_XMM3],
- &ia32_xmm_regs[REG_XMM4],
- &ia32_xmm_regs[REG_XMM5],
- &ia32_xmm_regs[REG_XMM6],
- &ia32_xmm_regs[REG_XMM7]
+ &ia32_registers[REG_XMM0],
+ &ia32_registers[REG_XMM1],
+ &ia32_registers[REG_XMM2],
+ &ia32_registers[REG_XMM3],
+ &ia32_registers[REG_XMM4],
+ &ia32_registers[REG_XMM5],
+ &ia32_registers[REG_XMM6],
+ &ia32_registers[REG_XMM7]
};
static const arch_register_t *fpreg_sse_param_reg_this[] = {
static void ia32_get_call_abi(const void *self, ir_type *method_type,
be_abi_call_t *abi)
{
- ir_type *tp;
- ir_mode *mode;
unsigned cc;
int n, i, regnum;
int pop_amount = 0;
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- ir_mode *mode;
- const arch_register_t *reg = NULL;
+ const arch_register_t *reg = NULL;
+ ir_type *tp = get_method_param_type(method_type, i);
+ ir_mode *mode = get_type_mode(tp);
- tp = get_method_param_type(method_type, i);
- mode = get_type_mode(tp);
if (mode != NULL) {
reg = ia32_get_RegParam_reg(cc, regnum, mode);
}
/* In case of 64bit returns, we will have two 32bit values */
if (n == 2) {
- tp = get_method_res_type(method_type, 0);
- mode = get_type_mode(tp);
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
assert(!mode_is_float(mode) && "two FP results not supported");
assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
- be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
- be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
+ be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
}
else if (n == 1) {
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
const arch_register_t *reg;
-
- tp = get_method_res_type(method_type, 0);
assert(is_atomic_type(tp));
- mode = get_type_mode(tp);
- reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
ir_node *mux_false)
{
- ir_node *cmp_l;
- ir_node *cmp_r;
- ir_node *cmp;
- pn_Cmp pnc;
+ ir_node *cmp_l;
+ ir_node *cmp_r;
+ ir_relation relation;
- if (!is_Proj(sel))
- return false;
- cmp = get_Proj_pred(sel);
- if (!is_Cmp(cmp))
+ if (!is_Cmp(sel))
return false;
- cmp_l = get_Cmp_left(cmp);
- cmp_r = get_Cmp_right(cmp);
+ cmp_l = get_Cmp_left(sel);
+ cmp_r = get_Cmp_right(sel);
if (!mode_is_float(get_irn_mode(cmp_l)))
return false;
* or max(a, b) = a >= b ? a : b
* (Note we only handle float min/max here)
*/
- pnc = get_Proj_proj(sel);
- switch (pnc) {
- case pn_Cmp_Ge:
- case pn_Cmp_Gt:
+ relation = get_Cmp_relation(sel);
+ switch (relation) {
+ case ir_relation_greater_equal:
+ case ir_relation_greater:
/* this is a max */
if (cmp_l == mux_true && cmp_r == mux_false)
return true;
break;
- case pn_Cmp_Le:
- case pn_Cmp_Lt:
+ case ir_relation_less_equal:
+ case ir_relation_less:
/* this is a min */
if (cmp_l == mux_true && cmp_r == mux_false)
return true;
break;
- case pn_Cmp_Uge:
- case pn_Cmp_Ug:
+ case ir_relation_unordered_greater_equal:
+ case ir_relation_unordered_greater:
/* this is a min */
if (cmp_l == mux_false && cmp_r == mux_true)
return true;
break;
- case pn_Cmp_Ule:
- case pn_Cmp_Ul:
+ case ir_relation_unordered_less_equal:
+ case ir_relation_unordered_less:
/* this is a max */
if (cmp_l == mux_false && cmp_r == mux_true)
return true;
return false;
if (is_Const(mux_true) && is_Const(mux_false)) {
- /* we can create a set plus up two 3 instructions for any combination of constants */
+ /* we can create a set plus up two 3 instructions for any combination
+ * of constants */
return true;
}
static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
{
- ir_node *cmp;
- ir_node *cmp_left;
- ir_node *cmp_right;
- ir_node *sub_left;
- ir_node *sub_right;
- ir_mode *mode;
- long pn;
-
- if (!is_Proj(sel))
- return false;
+ ir_node *cmp_left;
+ ir_node *cmp_right;
+ ir_node *sub_left;
+ ir_node *sub_right;
+ ir_mode *mode;
+ ir_relation relation;
- cmp = get_Proj_pred(sel);
- if (!is_Cmp(cmp))
+ if (!is_Cmp(sel))
return false;
mode = get_irn_mode(mux_true);
if (mode_is_signed(mode) || mode_is_float(mode))
return false;
- pn = get_Proj_proj(sel);
- cmp_left = get_Cmp_left(cmp);
- cmp_right = get_Cmp_right(cmp);
+ relation = get_Cmp_relation(sel);
+ cmp_left = get_Cmp_left(sel);
+ cmp_right = get_Cmp_right(sel);
/* "move" zero constant to false input */
if (is_Const(mux_true) && is_Const_null(mux_true)) {
ir_node *tmp = mux_false;
mux_false = mux_true;
mux_true = tmp;
- pn = get_negated_pnc(pn, mode);
+ relation = get_negated_relation(relation);
}
if (!is_Const(mux_false) || !is_Const_null(mux_false))
return false;
sub_right = get_Sub_right(mux_true);
/* Mux(a >=u b, 0, a-b) */
- if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
+ if ((relation & ir_relation_greater)
&& sub_left == cmp_left && sub_right == cmp_right)
return true;
/* Mux(a <=u b, 0, b-a) */
- if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
+ if ((relation & ir_relation_less)
&& sub_left == cmp_right && sub_right == cmp_left)
return true;
if (get_mode_size_bits(mode) > 32)
return false;
/* we can handle Abs for all modes and compares (except 64bit) */
- if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
+ if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
return true;
/* we can't handle MuxF yet */
if (mode_is_float(mode))
return true;
/* Check Cmp before the node */
- if (is_Proj(sel)) {
- ir_node *cmp = get_Proj_pred(sel);
- if (is_Cmp(cmp)) {
- ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
-
- /* we can't handle 64bit compares */
- if (get_mode_size_bits(cmp_mode) > 32)
- return false;
-
- /* we can't handle float compares */
- if (mode_is_float(cmp_mode))
- return false;
- }
+ if (is_Cmp(sel)) {
+ ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
+
+ /* we can't handle 64bit compares */
+ if (get_mode_size_bits(cmp_mode) > 32)
+ return false;
+
+ /* we can't handle float compares */
+ if (mode_is_float(cmp_mode))
+ return false;
}
/* did we disable cmov generation? */
return ia32_get_clobber_register(clobber) != NULL;
}
+static ir_node *ia32_create_set(ir_node *cond)
+{
+ /* ia32-set function produces 8-bit results which have to be converted */
+ ir_node *set = ir_create_mux_set(cond, mode_Bu);
+ ir_node *block = get_nodes_block(set);
+ return new_r_Conv(block, set, mode_Iu);
+}
+
static void ia32_lower_for_target(void)
{
- int n_irgs = get_irp_n_irgs();
- int i;
+ size_t i, n_irgs = get_irp_n_irgs();
lower_mode_b_config_t lower_mode_b_config = {
mode_Iu, /* lowered mode */
- mode_Bu, /* preferred mode for set */
+ ia32_create_set,
0, /* don't lower direct compares */
};
+ lower_params_t params = {
+ 4, /* def_ptr_alignment */
+ LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
+ ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
+ NULL, /* find pointer type */
+ NULL, /* ret_compound_in_regs */
+ };
/* perform doubleword lowering */
lwrdw_param_t lower_dw_params = {
ia32_create_intrinsic_fkt,
&intrinsic_env,
};
- lower_dw_ops(&lower_dw_params);
+
+ /* lower compound param handling */
+ lower_calls_with_compounds(¶ms);
+
+ ir_prepare_dw_lowering(&lower_dw_params);
+ ir_lower_dw_ops();
for (i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
/* lower for mode_b stuff */
ir_lower_mode_b(irg, &lower_mode_b_config);
/* break up switches with wide ranges */
- lower_switch(irg, 256, true);
+ lower_switch(irg, 4, 256, false);
}
}
*/
static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
{
- ir_node *st, *p = trampoline;
- ir_mode *mode = get_irn_mode(p);
+ ir_graph *irg = get_irn_irg(block);
+ ir_node *p = trampoline;
+ ir_mode *mode = get_irn_mode(p);
+ ir_node *st;
/* mov ecx,<env> */
- st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, env, 0);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ st = new_r_Store(block, mem, p, env, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
/* jmp <callee> */
- st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, callee, 0);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+ st = new_r_Store(block, mem, p, callee, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+ p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
return mem;
}
static const ir_settings_arch_dep_t ad = {
1, /* also use subs */
4, /* maximum shifts */
- 31, /* maximum shift amount */
+ 63, /* maximum shift amount */
ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* support inline assembly */
1, /* support Rotl nodes */
0, /* little endian */
- ia32_lower_for_target,
NULL, /* will be set later */
ia32_is_mux_allowed,
NULL, /* float arithmetic mode, will be set below */
return &p;
}
+/**
+ * Check if the given register is callee or caller save.
+ */
+static int ia32_register_saved_by(const arch_register_t *reg, int callee)
+{
+ if (callee) {
+ /* check for callee saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EBX:
+ case REG_GP_ESI:
+ case REG_GP_EDI:
+ case REG_GP_EBP:
+ return 1;
+ default:
+ return 0;
+ }
+ }
+ } else {
+ /* check for caller saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EDX:
+ case REG_GP_ECX:
+ case REG_GP_EAX:
+ return 1;
+ default:
+ return 0;
+ }
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ /* all XMM registers are caller save */
+ return reg->index != REG_XMM_NOREG;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
+ /* all VFP registers are caller save */
+ return reg->index != REG_VFP_NOREG;
+ }
+ }
+ return 0;
+}
+
static const lc_opt_enum_int_items_t gas_items[] = {
{ "elf", OBJECT_FILE_FORMAT_ELF },
{ "mingw", OBJECT_FILE_FORMAT_COFF },
#ifdef FIRM_GRGEN_BE
LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
#endif
- LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
- &ia32_isa_template.base.stack_alignment),
+ LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
+ &ia32_isa_template.base.stack_alignment),
+ LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
LC_OPT_LAST
};
const arch_isa_if_t ia32_isa_if = {
ia32_init,
+ ia32_lower_for_target,
ia32_done,
ia32_handle_intrinsics,
- ia32_get_n_reg_class,
- ia32_get_reg_class,
ia32_get_reg_class_for_mode,
ia32_get_call_abi,
ia32_get_reg_class_alignment,
ia32_after_ra, /* after register allocation hook */
ia32_finish, /* called before codegen */
ia32_emit, /* emit && done */
+ ia32_register_saved_by,
};
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
-
ia32_init_emitter();
ia32_init_finish();
ia32_init_optimize();
projects / libfirm / blobdiff