#include "lower_calls.h"
#include "lower_mode_b.h"
#include "lower_softfloat.h"
+#include "firmstat_t.h"
#include "beabi.h"
-#include "beirg.h"
#include "benode.h"
#include "belower.h"
#include "besched.h"
* The environment for the intrinsic mapping.
*/
static ia32_intrinsic_env_t intrinsic_env = {
- NULL, /* the isa */
- NULL, /* the irg, these entities belong to */
NULL, /* entity for __divdi3 library call */
NULL, /* entity for __moddi3 library call */
NULL, /* entity for __udivdi3 library call */
&ia32_registers[REG_GP_NOREG]);
}
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+ir_node *ia32_new_NoReg_fp(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
- &ia32_registers[REG_VFP_NOREG]);
+ return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
+ &ia32_registers[REG_FP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
if (ia32_cg_config.use_sse2) {
return ia32_new_NoReg_xmm(irg);
} else {
- return ia32_new_NoReg_vfp(irg);
+ return ia32_new_NoReg_fp(irg);
}
}
return cost;
}
-/**
- * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
- *
- * @param irn The original operation
- * @param i Index of the argument we want the inverse operation to yield
- * @param inverse struct to be filled with the resulting inverse op
- * @param obstack The obstack to use for allocation of the returned nodes array
- * @return The inverse operation or NULL if operation invertible
- */
-static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
-{
- (void) irn;
- (void) i;
- (void) inverse;
- (void) obst;
- return NULL;
-
-#if 0
- ir_mode *mode;
- ir_mode *irn_mode;
- ir_node *block, *noreg, *nomem;
- dbg_info *dbgi;
-
- /* we cannot invert non-ia32 irns */
- if (! is_ia32_irn(irn))
- return NULL;
-
- /* operand must always be a real operand (not base, index or mem) */
- if (i != n_ia32_binary_left && i != n_ia32_binary_right)
- return NULL;
-
- /* we don't invert address mode operations */
- if (get_ia32_op_type(irn) != ia32_Normal)
- return NULL;
-
- /* TODO: adjust for new immediates... */
- ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
- irn);
- return NULL;
-
- block = get_nodes_block(irn);
- mode = get_irn_mode(irn);
- irn_mode = get_irn_mode(irn);
- noreg = get_irn_n(irn, 0);
- nomem = get_irg_no_mem(irg);
- dbgi = get_irn_dbg_info(irn);
-
- /* initialize structure */
- inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
- inverse->costs = 0;
- inverse->n = 1;
-
- switch (get_ia32_irn_opcode(irn)) {
- case iro_ia32_Add:
- if (get_ia32_immop_type(irn) == ia32_ImmConst) {
- /* we have an add with a const here */
- /* invers == add with negated const */
- inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
- set_ia32_commutative(inverse->nodes[0]);
- }
- else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
- /* we have an add with a symconst here */
- /* invers == sub with const */
- inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += 2;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal add: inverse == sub */
- inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
- inverse->costs += 2;
- }
- break;
- case iro_ia32_Sub:
- if (get_ia32_immop_type(irn) != ia32_ImmNone) {
- /* we have a sub with a const/symconst here */
- /* invers == add with this const */
- inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal sub */
- if (i == n_ia32_binary_left) {
- inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
- }
- else {
- inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
- }
- inverse->costs += 1;
- }
- break;
- case iro_ia32_Xor:
- if (get_ia32_immop_type(irn) != ia32_ImmNone) {
- /* xor with const: inverse = xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
- inverse->costs += 1;
- }
- break;
- case iro_ia32_Not: {
- inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
- inverse->costs += 1;
- break;
- }
- case iro_ia32_Neg: {
- inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
- inverse->costs += 1;
- break;
- }
- default:
- /* inverse operation not supported */
- return NULL;
- }
-
- return inverse;
-#endif
-}
-
static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
if (mode_is_float(mode))
case ia32_am_binary:
switch (i) {
case n_ia32_binary_left: {
- const arch_register_req_t *req;
if (!is_ia32_commutative(irn))
return 0;
/* we can't swap left/right for limited registers
- * (As this (currently) breaks constraint handling copies)
- */
- req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
- if (req->type & arch_register_req_type_limited)
+ * (As this (currently) breaks constraint handling copies) */
+ arch_register_req_t const *const req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
+ if (arch_register_req_is(req, limited))
return 0;
break;
}
ia32_get_frame_entity,
ia32_set_frame_offset,
ia32_get_sp_bias,
- ia32_get_inverse,
ia32_get_op_estimated_cost,
ia32_possible_memory_operand,
ia32_perform_memory_operand,
};
-static ir_entity *mcount = NULL;
static int gprof = 0;
static void ia32_before_abi(ir_graph *irg)
{
if (gprof) {
+ static ir_entity *mcount = NULL;
if (mcount == NULL) {
ir_type *tp = new_type_method(0, 0);
ident *id = new_id_from_str("mcount");
default:
panic("Unknown AM type");
}
- noreg = ia32_new_NoReg_gp(current_ir_graph);
+ noreg = ia32_new_NoReg_gp(irg);
set_irn_n(node, n_ia32_base, noreg);
set_irn_n(node, n_ia32_index, noreg);
set_ia32_am_offs_int(node, 0);
/* rewire mem-proj */
if (get_irn_mode(node) == mode_T) {
- const ir_edge_t *edge;
foreach_out_edge(node, edge) {
ir_node *out = get_edge_src_irn(edge);
if (get_irn_mode(out) == mode_M) {
if (ia32_cg_config.use_sse2)
new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
} else {
- store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
- res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
+ res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
}
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
*/
static void transform_MemPerm(ir_node *node)
{
- ir_node *block = get_nodes_block(node);
- ir_graph *irg = get_irn_irg(node);
- ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
- int arity = be_get_MemPerm_entity_arity(node);
- ir_node **pops = ALLOCAN(ir_node*, arity);
- ir_node *in[1];
- ir_node *keep;
- int i;
- const ir_edge_t *edge;
- const ir_edge_t *next;
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
+ int arity = be_get_MemPerm_entity_arity(node);
+ ir_node **pops = ALLOCAN(ir_node*, arity);
+ ir_node *in[1];
+ ir_node *keep;
+ int i;
/* create Pushs */
for (i = 0; i < arity; ++i) {
sched_add_before(node, keep);
/* exchange memprojs */
- foreach_out_edge_safe(node, edge, next) {
+ foreach_out_edge_safe(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
int p = get_Proj_proj(proj);
break;
}
- case iro_ia32_vfild:
- case iro_ia32_vfld:
+ case iro_ia32_fild:
+ case iro_ia32_fld:
case iro_ia32_xLoad: {
mode = get_ia32_ls_mode(node);
align = 4;
case iro_ia32_Store8Bit:
case iro_ia32_Store:
case iro_ia32_fst:
- case iro_ia32_fstp:
- case iro_ia32_vfist:
- case iro_ia32_vfisttp:
- case iro_ia32_vfst:
+ case iro_ia32_fist:
+ case iro_ia32_fisttp:
case iro_ia32_xStore:
case iro_ia32_xStoreSimple:
#endif
ir_node *block = get_nodes_block(ret);
ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
ir_node *curr_sp = first_sp;
- ir_mode *mode_gp = mode_Iu;
+ ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
if (!layout->sp_relative) {
int n_ebp = determine_ebp_input(ret);
ir_node *mem = get_irg_initial_mem(irg);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
- ir_node *curr_bp = initial_bp;
- ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
+ ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
ir_node *incsp;
curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
- mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
arch_set_irn_register(curr_sp, sp);
sched_add_after(start, push);
/* move esp to ebp */
- curr_bp = be_new_Copy(block, curr_sp);
+ ir_node *const curr_bp = be_new_Copy(block, curr_sp);
sched_add_after(push, curr_bp);
be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
sched_add_after(curr_bp, curr_sp);
be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
- edges_reroute(initial_bp, curr_bp);
- set_irn_n(push, n_ia32_Push_val, initial_bp);
+ edges_reroute_except(initial_bp, curr_bp, push);
incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
- edges_reroute(initial_sp, incsp);
- set_irn_n(push, n_ia32_Push_stack, initial_sp);
+ edges_reroute_except(initial_sp, incsp, push);
sched_add_after(curr_sp, incsp);
/* make sure the initial IncSP is really used by someone */
layout->initial_bias = -4;
} else {
- ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
- edges_reroute(initial_sp, incsp);
- be_set_IncSP_pred(incsp, curr_sp);
+ ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
+ edges_reroute_except(initial_sp, incsp, incsp);
sched_add_after(start, incsp);
}
p = new_r_Add(block, p, one, mode);
st = new_r_Store(block, mem, p, callee, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, four, mode);
return mem;
}
*/
static ia32_isa_t ia32_isa_template = {
{
- &ia32_isa_if, /* isa interface implementation */
+ &ia32_isa_if, /* isa interface implementation */
N_IA32_REGISTERS,
ia32_registers,
N_IA32_CLASSES,
ia32_reg_classes,
- &ia32_registers[REG_ESP], /* stack pointer register */
- &ia32_registers[REG_EBP], /* base pointer register */
- &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
- 2, /* power of two stack alignment, 2^2 == 4 */
- NULL, /* main environment */
- 7, /* costs for a spill instruction */
- 5, /* costs for a reload instruction */
- false, /* no custom abi handling */
+ &ia32_registers[REG_ESP], /* stack pointer register */
+ &ia32_registers[REG_EBP], /* base pointer register */
+ 2, /* power of two stack alignment, 2^2 == 4 */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
+ false, /* no custom abi handling */
},
- NULL, /* tv_ents */
- IA32_FPU_ARCH_X87, /* FPU architecture */
+ NULL, /* tv_ents */
+ IA32_FPU_ARCH_X87, /* FPU architecture */
};
-static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
+static arch_env_t *ia32_begin_codegeneration(void)
{
ia32_isa_t *isa = XMALLOC(ia32_isa_t);
*isa = ia32_isa_template;
isa->tv_ent = pmap_create();
- /* enter the ISA object into the intrinsic environment */
- intrinsic_env.isa = isa;
-
- be_emit_init(env->file_handle);
- be_gas_begin_compilation_unit(env);
-
return &isa->base;
}
static void ia32_end_codegeneration(void *self)
{
ia32_isa_t *isa = (ia32_isa_t*)self;
-
- /* emit now all global declarations */
- be_gas_end_compilation_unit(isa->base.main_env);
-
- be_emit_exit();
-
pmap_destroy(isa->tv_ent);
free(self);
}
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
/* set abi flags for calls */
- /* call_flags.bits.try_omit_fp not changed: can handle both settings */
- call_flags.bits.call_has_imm = false; /* No call immediate, we handle this by ourselves */
+ /* call_flags.try_omit_fp not changed: can handle both settings */
+ call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
/* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
const arch_register_t *reg;
assert(is_atomic_type(tp));
- reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
static void ia32_lower_for_target(void)
{
+ ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
size_t i, n_irgs = get_irp_n_irgs();
/* perform doubleword lowering */
lower_floating_point();
}
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* break up switches with wide ranges */
+ lower_switch(irg, 4, 256, mode_gp);
+ }
+
ir_prepare_dw_lowering(&lower_dw_params);
ir_lower_dw_ops();
ir_graph *irg = get_irp_irg(i);
/* lower for mode_b stuff */
ir_lower_mode_b(irg, mode_Iu);
- /* break up switches with wide ranges */
- lower_switch(irg, 4, 256, false);
}
for (i = 0; i < n_irgs; ++i) {
} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
/* all XMM registers are caller save */
return reg->index != REG_XMM_NOREG;
- } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
- /* all VFP registers are caller save */
- return reg->index != REG_VFP_NOREG;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
+ /* all FP registers are caller save */
+ return reg->index != REG_FP_NOREG;
}
}
return 0;
projects / libfirm / blobdiff