* @file
* @brief This is the main ia32 firm backend driver.
* @author Christian Wuerdig
- * @version $Id$
*/
#include "config.h"
#include "irflag.h"
#include "irgmod.h"
#include "irgopt.h"
-#include "irbitset.h"
#include "irgopt.h"
#include "irdump.h"
#include "pdeq.h"
#include "iroptimize.h"
#include "instrument.h"
#include "iropt_t.h"
-
-#include "../beabi.h"
-#include "../beirg.h"
-#include "../benode.h"
-#include "../belower.h"
-#include "../besched.h"
+#include "lower_dw.h"
+#include "lower_calls.h"
+#include "lower_mode_b.h"
+#include "lower_softfloat.h"
+#include "firmstat_t.h"
+
+#include "beabi.h"
+#include "benode.h"
+#include "belower.h"
+#include "besched.h"
#include "be.h"
-#include "../be_t.h"
-#include "../beirgmod.h"
-#include "../be_dbgout.h"
-#include "../beblocksched.h"
-#include "../bemachine.h"
-#include "../bespillslots.h"
-#include "../bemodule.h"
-#include "../begnuas.h"
-#include "../bestate.h"
-#include "../beflags.h"
-#include "../betranshlp.h"
-#include "../belistsched.h"
-#include "../beabihelper.h"
+#include "be_t.h"
+#include "beirgmod.h"
+#include "beblocksched.h"
+#include "bespillutil.h"
+#include "bespillslots.h"
+#include "bemodule.h"
+#include "begnuas.h"
+#include "bestate.h"
+#include "beflags.h"
+#include "betranshlp.h"
+#include "belistsched.h"
+#include "beabihelper.h"
+#include "bestack.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
-#include "gen_ia32_machine.h"
#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_emitter.h"
#include "ia32_x87.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
-#include "ia32_util.h"
#include "ia32_fpu.h"
#include "ia32_architecture.h"
transformer_t be_transformer = TRANSFORMER_DEFAULT;
#endif
-DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-
-ir_mode *ia32_mode_fpcw = NULL;
+ir_mode *ia32_mode_fpcw;
+ir_mode *ia32_mode_E;
+ir_type *ia32_type_E;
/** The current omit-fp state */
-static unsigned ia32_curr_fp_ommitted = 0;
static ir_type *omit_fp_between_type = NULL;
static ir_type *between_type = NULL;
static ir_entity *old_bp_ent = NULL;
* The environment for the intrinsic mapping.
*/
static ia32_intrinsic_env_t intrinsic_env = {
- NULL, /* the isa */
- NULL, /* the irg, these entities belong to */
NULL, /* entity for __divdi3 library call */
NULL, /* entity for __moddi3 library call */
NULL, /* entity for __udivdi3 library call */
};
-typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
+typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
/**
* Used to create per-graph unique pseudo nodes.
&ia32_registers[REG_GP_NOREG]);
}
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+ir_node *ia32_new_NoReg_fp(ir_graph *irg)
{
ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
- &ia32_registers[REG_VFP_NOREG]);
+ return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
+ &ia32_registers[REG_FP_NOREG]);
}
ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
{
ir_graph *irg = get_irn_irg(irn);
- const arch_register_req_t *req = arch_get_register_req(irn, pos);
+ const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
assert(req != NULL && "Missing register requirements");
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
if (ia32_cg_config.use_sse2) {
return ia32_new_NoReg_xmm(irg);
} else {
- return ia32_new_NoReg_vfp(irg);
+ return ia32_new_NoReg_fp(irg);
}
}
-static arch_irn_class_t ia32_classify(const ir_node *irn)
-{
- arch_irn_class_t classification = arch_irn_class_none;
-
- assert(is_ia32_irn(irn));
-
- if (is_ia32_is_reload(irn))
- classification |= arch_irn_class_reload;
-
- if (is_ia32_is_spill(irn))
- classification |= arch_irn_class_spill;
-
- if (is_ia32_is_remat(irn))
- classification |= arch_irn_class_remat;
-
- return classification;
-}
-
-/**
- * The IA32 ABI callback object.
- */
-typedef struct {
- be_abi_call_flags_bits_t flags; /**< The call flags. */
- ir_graph *irg; /**< The associated graph. */
-} ia32_abi_env_t;
-
static ir_entity *ia32_get_frame_entity(const ir_node *irn)
{
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
if (is_ia32_Pop(node) || is_ia32_PopMem(node))
return -4;
- return 0;
-}
-
-/**
- * Generate the routine prologue.
- *
- * @param self The callback object.
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @param stack_bias Points to the current stack bias, can be modified if needed.
- *
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
-{
- ia32_abi_env_t *env = (ia32_abi_env_t*)self;
- ir_graph *irg = env->irg;
- const arch_env_t *arch_env = be_get_irg_arch_env(irg);
-
- ia32_curr_fp_ommitted = env->flags.try_omit_fp;
- if (! env->flags.try_omit_fp) {
- ir_node *bl = get_irg_start_block(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
- ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *push;
-
- /* mark bp register as ignore */
- be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
- get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
-
- /* push ebp */
- push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
- arch_irn_add_flags(push, arch_irn_flags_prolog);
- curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
- *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
-
- /* the push must have SP out register */
- arch_set_irn_register(curr_sp, arch_env->sp);
-
- /* this modifies the stack bias, because we pushed 32bit */
- *stack_bias -= 4;
-
- /* move esp to ebp */
- curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
- arch_irn_add_flags(curr_bp, arch_irn_flags_prolog);
- be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
- arch_register_req_type_ignore);
-
- /* beware: the copy must be done before any other sp use */
- curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
- arch_irn_add_flags(curr_sp, arch_irn_flags_prolog);
- be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
- arch_register_req_type_produces_sp);
-
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-
- return arch_env->bp;
+ if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
+ return SP_BIAS_RESET;
}
- return arch_env->sp;
-}
-
-/**
- * Generate the routine epilogue.
- * @param self The callback object.
- * @param bl The block for the epilog
- * @param mem A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
- * @return The register which shall be used as a stack frame base.
- *
- * All nodes which define registers in @p reg_map must keep @p reg_map current.
- */
-static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
-{
- ia32_abi_env_t *env = (ia32_abi_env_t*)self;
- const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
-
- if (env->flags.try_omit_fp) {
- /* simply remove the stack frame here */
- curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
- arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
- } else {
- ir_mode *mode_bp = arch_env->bp->reg_class->mode;
-
- if (ia32_cg_config.use_leave) {
- ir_node *leave;
-
- /* leave */
- leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
- curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
- curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
- arch_irn_add_flags(leave, arch_irn_flags_epilog);
- } else {
- ir_node *pop;
-
- /* copy ebp to esp */
- curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
- arch_set_irn_register(curr_sp, arch_env->sp);
- be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
- arch_register_req_type_ignore);
- arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
-
- /* pop ebp */
- pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
- curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
- curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
- arch_irn_add_flags(pop, arch_irn_flags_epilog);
-
- *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
- }
- arch_set_irn_register(curr_sp, arch_env->sp);
- arch_set_irn_register(curr_bp, arch_env->bp);
- }
-
- be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
- be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
-}
-
-/**
- * Initialize the callback object.
- * @param call The call object.
- * @param irg The graph with the method.
- * @return Some pointer. This pointer is passed to all other callback functions as self object.
- */
-static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
-{
- ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- return env;
-}
-
-/**
- * Destroy the callback object.
- * @param self The callback object.
- */
-static void ia32_abi_done(void *self)
-{
- free(self);
+ return 0;
}
/**
static void ia32_build_between_type(void)
{
#define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
- if (! between_type) {
+ if (between_type == NULL) {
ir_type *old_bp_type = new_type_primitive(mode_Iu);
ir_type *ret_addr_type = new_type_primitive(mode_Iu);
* it will contain the return address and space to store the old base pointer.
* @return The Firm type modeling the ABI between type.
*/
-static ir_type *ia32_abi_get_between_type(void *self)
+static ir_type *ia32_abi_get_between_type(ir_graph *irg)
{
- ia32_abi_env_t *env = (ia32_abi_env_t*)self;
-
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
+ return layout->sp_relative ? omit_fp_between_type : between_type;
}
/**
* Return the stack entity that contains the return address.
*/
-ir_entity *ia32_get_return_address_entity(void)
+ir_entity *ia32_get_return_address_entity(ir_graph *irg)
{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
+ return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
}
/**
* Return the stack entity that contains the frame address.
*/
-ir_entity *ia32_get_frame_address_entity(void)
+ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
{
+ const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ia32_build_between_type();
- return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
+ return layout->sp_relative ? NULL : old_bp_ent;
}
/**
return cost;
}
-/**
- * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
- *
- * @param irn The original operation
- * @param i Index of the argument we want the inverse operation to yield
- * @param inverse struct to be filled with the resulting inverse op
- * @param obstack The obstack to use for allocation of the returned nodes array
- * @return The inverse operation or NULL if operation invertible
- */
-static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
-{
- (void) irn;
- (void) i;
- (void) inverse;
- (void) obst;
- return NULL;
-
-#if 0
- ir_mode *mode;
- ir_mode *irn_mode;
- ir_node *block, *noreg, *nomem;
- dbg_info *dbg;
-
- /* we cannot invert non-ia32 irns */
- if (! is_ia32_irn(irn))
- return NULL;
-
- /* operand must always be a real operand (not base, index or mem) */
- if (i != n_ia32_binary_left && i != n_ia32_binary_right)
- return NULL;
-
- /* we don't invert address mode operations */
- if (get_ia32_op_type(irn) != ia32_Normal)
- return NULL;
-
- /* TODO: adjust for new immediates... */
- ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
- irn);
- return NULL;
-
- block = get_nodes_block(irn);
- mode = get_irn_mode(irn);
- irn_mode = get_irn_mode(irn);
- noreg = get_irn_n(irn, 0);
- nomem = new_r_NoMem(irg);
- dbg = get_irn_dbg_info(irn);
-
- /* initialize structure */
- inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
- inverse->costs = 0;
- inverse->n = 1;
-
- switch (get_ia32_irn_opcode(irn)) {
- case iro_ia32_Add:
-#if 0
- if (get_ia32_immop_type(irn) == ia32_ImmConst) {
- /* we have an add with a const here */
- /* invers == add with negated const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
- set_ia32_commutative(inverse->nodes[0]);
- }
- else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
- /* we have an add with a symconst here */
- /* invers == sub with const */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += 2;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal add: inverse == sub */
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
- inverse->costs += 2;
- }
-#endif
- break;
- case iro_ia32_Sub:
-#if 0
- if (get_ia32_immop_type(irn) != ia32_ImmNone) {
- /* we have a sub with a const/symconst here */
- /* invers == add with this const */
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal sub */
- if (i == n_ia32_binary_left) {
- inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
- }
- else {
- inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
- }
- inverse->costs += 1;
- }
-#endif
- break;
- case iro_ia32_Xor:
-#if 0
- if (get_ia32_immop_type(irn) != ia32_ImmNone) {
- /* xor with const: inverse = xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
- inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
- copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
- }
- else {
- /* normal xor */
- inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
- inverse->costs += 1;
- }
-#endif
- break;
- case iro_ia32_Not: {
- inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
- inverse->costs += 1;
- break;
- }
- case iro_ia32_Neg: {
- inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
- inverse->costs += 1;
- break;
- }
- default:
- /* inverse operation not supported */
- return NULL;
- }
-
- return inverse;
-#endif
-}
-
static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
if (mode_is_float(mode))
case ia32_am_binary:
switch (i) {
case n_ia32_binary_left: {
- const arch_register_req_t *req;
if (!is_ia32_commutative(irn))
return 0;
/* we can't swap left/right for limited registers
- * (As this (currently) breaks constraint handling copies)
- */
- req = arch_get_in_register_req(irn, n_ia32_binary_left);
- if (req->type & arch_register_req_type_limited)
+ * (As this (currently) breaks constraint handling copies) */
+ arch_register_req_t const *const req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
+ if (arch_register_req_is(req, limited))
return 0;
break;
}
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
- ia32_abi_init,
- ia32_abi_done,
ia32_abi_get_between_type,
- ia32_abi_prologue,
- ia32_abi_epilogue
};
/* register allocator interface */
static const arch_irn_ops_t ia32_irn_ops = {
- ia32_classify,
ia32_get_frame_entity,
ia32_set_frame_offset,
ia32_get_sp_bias,
- ia32_get_inverse,
ia32_get_op_estimated_cost,
ia32_possible_memory_operand,
ia32_perform_memory_operand,
};
-static ir_entity *mcount = NULL;
static int gprof = 0;
static void ia32_before_abi(ir_graph *irg)
{
if (gprof) {
+ static ir_entity *mcount = NULL;
if (mcount == NULL) {
ir_type *tp = new_type_method(0, 0);
ident *id = new_id_from_str("mcount");
/* do local optimizations (mainly CSE) */
optimize_graph_df(irg);
+ /* backend code expects that outedges are always enabled */
+ assure_edges(irg);
if (irg_data->dump)
dump_ir_graph(irg, "transformed");
/* do code placement, to optimize the position of constants */
place_code(irg);
+ /* backend code expects that outedges are always enabled */
+ assure_edges(irg);
if (irg_data->dump)
dump_ir_graph(irg, "place");
ir_graph *irg = get_irn_irg(node);
ir_node *block = get_nodes_block(node);
ir_node *base = get_irn_n(node, n_ia32_base);
- ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *idx = get_irn_n(node, n_ia32_index);
ir_node *mem = get_irn_n(node, n_ia32_mem);
ir_node *noreg;
- ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
+ ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
if (is_ia32_is_reload(node))
set_ia32_is_reload(load);
- set_irn_n(node, n_ia32_mem, new_r_NoMem(irg));
+ set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
switch (get_ia32_am_support(node)) {
case ia32_am_unary:
default:
panic("Unknown AM type");
}
- noreg = ia32_new_NoReg_gp(current_ir_graph);
+ noreg = ia32_new_NoReg_gp(irg);
set_irn_n(node, n_ia32_base, noreg);
set_irn_n(node, n_ia32_index, noreg);
set_ia32_am_offs_int(node, 0);
/* rewire mem-proj */
if (get_irn_mode(node) == mode_T) {
- const ir_edge_t *edge;
foreach_out_edge(node, edge) {
ir_node *out = get_edge_src_irn(edge);
if (get_irn_mode(out) == mode_M) {
case ia32_AddrModeD:
/* TODO implement this later... */
panic("found DestAM with flag user %+F this should not happen", node);
- break;
default: assert(type == ia32_Normal); break;
}
static void transform_to_Load(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(irg);
- ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
+ ir_node *mem = get_irn_n(node, n_be_Reload_mem);
ir_node *new_op, *proj;
const arch_register_t *reg;
if (mode_is_float(spillmode)) {
if (ia32_cg_config.use_sse2)
- new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
else
- new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
+ new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
}
else if (get_mode_size_bits(spillmode) == 128) {
/* Reload 128 bit SSE registers */
- new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
}
else
- new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
+ new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, spillmode);
DBG_OPT_RELOAD2LD(node, new_op);
- proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
+ proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
static void transform_to_Store(ir_node *node)
{
ir_graph *irg = get_irn_irg(node);
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
- const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
+ const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
ir_mode *mode = get_spill_mode(spillval);
ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *nomem = new_r_NoMem(irg);
+ ir_node *nomem = get_irg_no_mem(irg);
ir_node *ptr = get_irg_frame(irg);
- ir_node *val = get_irn_n(node, be_pos_Spill_val);
+ ir_node *val = get_irn_n(node, n_be_Spill_val);
+ ir_node *res;
ir_node *store;
ir_node *sched_point = NULL;
}
if (mode_is_float(mode)) {
- if (ia32_cg_config.use_sse2)
- store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
- else
- store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
+ if (ia32_cg_config.use_sse2) {
+ store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
+ } else {
+ store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
+ res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
+ }
} else if (get_mode_size_bits(mode) == 128) {
/* Spill 128 bit SSE registers */
- store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
} else {
- store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
+ store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
+ res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
}
set_ia32_op_type(store, ia32_AddrModeD);
sched_remove(node);
}
- exchange(node, store);
+ exchange(node, res);
}
static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_graph *irg = get_irn_irg(node);
- ir_node *noreg = ia32_new_NoReg_gp(irg);
- ir_node *frame = get_irg_frame(irg);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
+ ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
{
- dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_irn_irg(node);
ir_node *noreg = ia32_new_NoReg_gp(irg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_r_NoMem(irg), sp);
+ ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
+ get_irg_no_mem(irg), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_mode *spmode = mode_Iu;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *spmode = mode_Iu;
const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
- sp = new_rd_Proj(dbg, pred, spmode, pos);
+ sp = new_rd_Proj(dbgi, pred, spmode, pos);
arch_set_irn_register(sp, spreg);
return sp;
*/
static void transform_MemPerm(ir_node *node)
{
- ir_node *block = get_nodes_block(node);
- ir_graph *irg = get_irn_irg(node);
- ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_registers[REG_ESP]);
- int arity = be_get_MemPerm_entity_arity(node);
- ir_node **pops = ALLOCAN(ir_node*, arity);
- ir_node *in[1];
- ir_node *keep;
- int i;
- const ir_edge_t *edge;
- const ir_edge_t *next;
+ ir_node *block = get_nodes_block(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
+ int arity = be_get_MemPerm_entity_arity(node);
+ ir_node **pops = ALLOCAN(ir_node*, arity);
+ ir_node *in[1];
+ ir_node *keep;
+ int i;
/* create Pushs */
for (i = 0; i < arity; ++i) {
sp = create_spproj(node, push, pn_ia32_Push_stack);
}
- set_irn_n(node, i, new_r_Bad(irg));
+ set_irn_n(node, i, new_r_Bad(irg, mode_X));
}
/* create pops */
sched_add_before(node, keep);
/* exchange memprojs */
- foreach_out_edge_safe(node, edge, next) {
+ foreach_out_edge_safe(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
int p = get_Proj_proj(proj);
}
/* remove memperm */
- arity = get_irn_arity(node);
- for (i = 0; i < arity; ++i) {
- set_irn_n(node, i, new_r_Bad(irg));
- }
sched_remove(node);
+ kill_node(node);
}
/**
break;
}
- case iro_ia32_vfild:
- case iro_ia32_vfld:
+ case iro_ia32_fild:
+ case iro_ia32_fld:
case iro_ia32_xLoad: {
mode = get_ia32_ls_mode(node);
align = 4;
case iro_ia32_Store8Bit:
case iro_ia32_Store:
case iro_ia32_fst:
- case iro_ia32_fstp:
- case iro_ia32_vfist:
- case iro_ia32_vfisttp:
- case iro_ia32_vfst:
+ case iro_ia32_fist:
+ case iro_ia32_fisttp:
case iro_ia32_xStore:
case iro_ia32_xStoreSimple:
#endif
be_node_needs_frame_entity(env, node, mode, align);
}
+static int determine_ebp_input(ir_node *ret)
+{
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ int arity = get_irn_arity(ret);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *input = get_irn_n(ret, i);
+ if (arch_get_irn_register(input) == bp)
+ return i;
+ }
+ panic("no ebp input found at %+F", ret);
+}
+
+static void introduce_epilog(ir_node *ret)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_graph *irg = get_irn_irg(ret);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *block = get_nodes_block(ret);
+ ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
+ ir_node *curr_sp = first_sp;
+ ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
+
+ if (!layout->sp_relative) {
+ int n_ebp = determine_ebp_input(ret);
+ ir_node *curr_bp = get_irn_n(ret, n_ebp);
+ if (ia32_cg_config.use_leave) {
+ ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
+ curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, leave);
+ } else {
+ ir_node *pop;
+ ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
+ /* copy ebp to esp */
+ curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, curr_sp);
+
+ /* pop ebp */
+ pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
+ curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
+ curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
+ curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
+ arch_set_irn_register(curr_bp, bp);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_before(ret, pop);
+
+ set_irn_n(ret, n_be_Return_mem, curr_mem);
+ }
+ set_irn_n(ret, n_ebp, curr_bp);
+ } else {
+ ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
+ sched_add_before(ret, incsp);
+ curr_sp = incsp;
+ }
+ set_irn_n(ret, n_be_Return_sp, curr_sp);
+
+ /* keep verifier happy... */
+ if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
+ kill_node(first_sp);
+ }
+}
+
/**
- * We transform Spill and Reload here. This needs to be done before
- * stack biasing otherwise we would miss the corrected offset for these nodes.
+ * put the Prolog code at the beginning, epilog code before each return
*/
-static void ia32_after_ra(ir_graph *irg)
-{
- be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+static void introduce_prolog_epilog(ir_graph *irg)
+{
+ const arch_register_t *sp = &ia32_registers[REG_ESP];
+ const arch_register_t *bp = &ia32_registers[REG_EBP];
+ ir_node *start = get_irg_start(irg);
+ ir_node *block = get_nodes_block(start);
+ ir_type *frame_type = get_irg_frame_type(irg);
+ unsigned frame_size = get_type_size_bytes(frame_type);
+ be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
+ ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
+ ir_node *curr_sp = initial_sp;
+ ir_mode *mode_gp = mode_Iu;
+
+ if (!layout->sp_relative) {
+ /* push ebp */
+ ir_node *mem = get_irg_initial_mem(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(irg);
+ ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
+ ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
+ ir_node *incsp;
- /* create and coalesce frame entities */
- irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
- be_assign_entities(fec_env, ia32_set_frame_entity);
- be_free_frame_entity_coalescer(fec_env);
+ curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
+ arch_set_irn_register(curr_sp, sp);
+ sched_add_after(start, push);
- irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
+ /* move esp to ebp */
+ ir_node *const curr_bp = be_new_Copy(block, curr_sp);
+ sched_add_after(push, curr_bp);
+ be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
+ curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
+ sched_add_after(curr_bp, curr_sp);
+ be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
+ edges_reroute_except(initial_bp, curr_bp, push);
+
+ incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
+ edges_reroute_except(initial_sp, incsp, push);
+ sched_add_after(curr_sp, incsp);
+
+ /* make sure the initial IncSP is really used by someone */
+ if (get_irn_n_edges(incsp) <= 1) {
+ ir_node *in[] = { incsp };
+ ir_node *keep = be_new_Keep(block, 1, in);
+ sched_add_after(incsp, keep);
+ }
+
+ layout->initial_bias = -4;
+ } else {
+ ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
+ edges_reroute_except(initial_sp, incsp, incsp);
+ sched_add_after(start, incsp);
+ }
+
+ /* introduce epilog for every return node */
+ {
+ ir_node *end_block = get_irg_end_block(irg);
+ int arity = get_irn_arity(end_block);
+ int i;
+
+ for (i = 0; i < arity; ++i) {
+ ir_node *ret = get_irn_n(end_block, i);
+ assert(be_is_Return(ret));
+ introduce_epilog(ret);
+ }
+ }
}
/**
* virtual with real x87 instructions, creating a block schedule and peephole
* optimisations.
*/
-static void ia32_finish(ir_graph *irg)
+static void ia32_finish_graph(ir_graph *irg)
{
- ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
+ bool at_begin = stack_layout->sp_relative ? true : false;
+ be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
+
+ /* create and coalesce frame entities */
+ irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
+ be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
+ be_free_frame_entity_coalescer(fec_env);
+
+ irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
+
+ introduce_prolog_epilog(irg);
+ /* fix stack entity offsets */
+ be_abi_fix_stack_nodes(irg);
+ be_abi_fix_stack_bias(irg);
+
+ /* fix 2-address code constraints */
ia32_finish_irg(irg);
/* we might have to rewrite x87 virtual registers */
/* do peephole optimisations */
ia32_peephole_optimization(irg);
+ be_remove_dead_nodes_from_schedule(irg);
+
/* create block schedule, this also removes empty blocks which might
* produce critical edges */
irg_data->blk_sched = be_create_block_schedule(irg);
struct obstack *obst = be_get_be_obst(irg);
ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
- irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
+ irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
if (gprof) {
/* Linux gprof implementation needs base pointer */
- be_get_irg_options(irg)->omit_fp = 0;
+ be_options.omit_fp = 0;
}
be_birg_from_irg(irg)->isa_link = irg_data;
}
-
-/**
- * Set output modes for GCC
- */
static const tarval_mode_info mo_integer = {
TVO_HEX,
"0x",
{
size_t i;
- for (i = get_irp_n_modes(); i > 0;) {
- ir_mode *mode = get_irp_mode(--i);
+ for (i = ir_get_n_modes(); i > 0;) {
+ ir_mode *mode = ir_get_mode(--i);
if (mode_is_int(mode))
set_tarval_mode_output_option(mode, &mo_integer);
extern const arch_isa_if_t ia32_isa_if;
-/**
- * The template that generates a new ISA object.
- * Note that this template can be changed by command line
- * arguments.
- */
-static ia32_isa_t ia32_isa_template = {
- {
- &ia32_isa_if, /* isa interface implementation */
- N_IA32_REGISTERS,
- ia32_registers,
- N_IA32_CLASSES,
- ia32_reg_classes,
- &ia32_registers[REG_ESP], /* stack pointer register */
- &ia32_registers[REG_EBP], /* base pointer register */
- &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
- -1, /* stack direction */
- 2, /* power of two stack alignment, 2^2 == 4 */
- NULL, /* main environment */
- 7, /* costs for a spill instruction */
- 5, /* costs for a reload instruction */
- false, /* no custom abi handling */
- },
- NULL, /* types */
- NULL, /* tv_ents */
- NULL, /* abstract machine */
-};
-
static void init_asm_constraints(void)
{
be_init_default_asm_constraint_flags();
}
/**
- * Initializes the backend ISA.
+ * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
*/
-static arch_env_t *ia32_init(FILE *file_handle)
+static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
+ ir_node *mux_false)
{
- ia32_isa_t *isa = XMALLOC(ia32_isa_t);
- size_t i, n;
+ ir_node *cmp_l;
+ ir_node *cmp_r;
+ ir_relation relation;
- set_tarval_output_modes();
+ if (!is_Cmp(sel))
+ return false;
- memcpy(isa, &ia32_isa_template, sizeof(*isa));
+ cmp_l = get_Cmp_left(sel);
+ cmp_r = get_Cmp_right(sel);
+ if (!mode_is_float(get_irn_mode(cmp_l)))
+ return false;
+
+ /* check for min/max. They're defined as (C-Semantik):
+ * min(a, b) = a < b ? a : b
+ * or min(a, b) = a <= b ? a : b
+ * max(a, b) = a > b ? a : b
+ * or max(a, b) = a >= b ? a : b
+ * (Note we only handle float min/max here)
+ */
+ relation = get_Cmp_relation(sel);
+ switch (relation) {
+ case ir_relation_greater_equal:
+ case ir_relation_greater:
+ /* this is a max */
+ if (cmp_l == mux_true && cmp_r == mux_false)
+ return true;
+ break;
+ case ir_relation_less_equal:
+ case ir_relation_less:
+ /* this is a min */
+ if (cmp_l == mux_true && cmp_r == mux_false)
+ return true;
+ break;
+ case ir_relation_unordered_greater_equal:
+ case ir_relation_unordered_greater:
+ /* this is a min */
+ if (cmp_l == mux_false && cmp_r == mux_true)
+ return true;
+ break;
+ case ir_relation_unordered_less_equal:
+ case ir_relation_unordered_less:
+ /* this is a max */
+ if (cmp_l == mux_false && cmp_r == mux_true)
+ return true;
+ break;
- if (ia32_mode_fpcw == NULL) {
- ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ default:
+ break;
}
- ia32_register_init();
- ia32_create_opcodes(&ia32_irn_ops);
+ return false;
+}
- be_emit_init(file_handle);
- isa->types = pmap_create();
- isa->tv_ent = pmap_create();
- isa->cpu = ia32_init_machine_description();
+static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+ ir_mode *mode = get_irn_mode(mux_true);
+ (void) sel;
- /* enter the ISA object into the intrinsic environment */
- intrinsic_env.isa = isa;
+ if (!mode_is_int(mode) && !mode_is_reference(mode)
+ && mode != mode_b)
+ return false;
- /* emit asm includes */
- n = get_irp_n_asms();
- for (i = 0; i < n; ++i) {
- be_emit_cstring("#APP\n");
- be_emit_ident(get_irp_asm(i));
- be_emit_cstring("\n#NO_APP\n");
+ if (is_Const(mux_true) && is_Const(mux_false)) {
+ /* we can create a set plus up two 3 instructions for any combination
+ * of constants */
+ return true;
}
- /* needed for the debug support */
- be_gas_emit_switch_section(GAS_SECTION_TEXT);
- be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
- be_emit_write_line();
-
- return &isa->base;
+ return false;
}
+static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
+ ir_node *mux_false)
+{
+ (void) sel;
+ if (!mode_is_float(get_irn_mode(mux_true)))
+ return false;
+
+ return is_Const(mux_true) && is_Const(mux_false);
+}
+
+static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+ ir_node *cmp_left;
+ ir_node *cmp_right;
+ ir_node *sub_left;
+ ir_node *sub_right;
+ ir_mode *mode;
+ ir_relation relation;
+
+ if (!is_Cmp(sel))
+ return false;
+
+ mode = get_irn_mode(mux_true);
+ if (mode_is_signed(mode) || mode_is_float(mode))
+ return false;
+
+ relation = get_Cmp_relation(sel);
+ cmp_left = get_Cmp_left(sel);
+ cmp_right = get_Cmp_right(sel);
+
+ /* "move" zero constant to false input */
+ if (is_Const(mux_true) && is_Const_null(mux_true)) {
+ ir_node *tmp = mux_false;
+ mux_false = mux_true;
+ mux_true = tmp;
+ relation = get_negated_relation(relation);
+ }
+ if (!is_Const(mux_false) || !is_Const_null(mux_false))
+ return false;
+ if (!is_Sub(mux_true))
+ return false;
+ sub_left = get_Sub_left(mux_true);
+ sub_right = get_Sub_right(mux_true);
+
+ /* Mux(a >=u b, 0, a-b) */
+ if ((relation & ir_relation_greater)
+ && sub_left == cmp_left && sub_right == cmp_right)
+ return true;
+ /* Mux(a <=u b, 0, b-a) */
+ if ((relation & ir_relation_less)
+ && sub_left == cmp_right && sub_right == cmp_left)
+ return true;
+
+ return false;
+}
+
+static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+ ir_node *mux_true)
+{
+ ir_mode *mode;
+
+ /* middleend can handle some things */
+ if (ir_is_optimizable_mux(sel, mux_false, mux_true))
+ return true;
+ /* we can handle Set for all modes and compares */
+ if (mux_is_set(sel, mux_true, mux_false))
+ return true;
+ /* SSE has own min/max operations */
+ if (ia32_cg_config.use_sse2
+ && mux_is_float_min_max(sel, mux_true, mux_false))
+ return true;
+ /* we can handle Mux(?, Const[f], Const[f]) */
+ if (mux_is_float_const_const(sel, mux_true, mux_false)) {
+#ifdef FIRM_GRGEN_BE
+ /* well, some code selectors can't handle it */
+ if (be_transformer != TRANSFORMER_PBQP
+ || be_transformer != TRANSFORMER_RAND)
+ return true;
+#else
+ return true;
+#endif
+ }
+
+ /* no support for 64bit inputs to cmov */
+ mode = get_irn_mode(mux_true);
+ if (get_mode_size_bits(mode) > 32)
+ return false;
+ /* we can handle Abs for all modes and compares (except 64bit) */
+ if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
+ return true;
+ /* we can't handle MuxF yet */
+ if (mode_is_float(mode))
+ return false;
+
+ if (mux_is_doz(sel, mux_true, mux_false))
+ return true;
+
+ /* Check Cmp before the node */
+ if (is_Cmp(sel)) {
+ ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
+
+ /* we can't handle 64bit compares */
+ if (get_mode_size_bits(cmp_mode) > 32)
+ return false;
+
+ /* we can't handle float compares */
+ if (mode_is_float(cmp_mode))
+ return false;
+ }
+
+ /* did we disable cmov generation? */
+ if (!ia32_cg_config.use_cmov)
+ return false;
+
+ /* we can use a cmov */
+ return true;
+}
/**
- * Closes the output file and frees the ISA structure.
+ * Create the trampoline code.
*/
-static void ia32_done(void *self)
+static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
{
- ia32_isa_t *isa = (ia32_isa_t*)self;
+ ir_graph *const irg = get_irn_irg(block);
+ ir_node * p = trampoline;
+ ir_mode *const mode = get_irn_mode(p);
+ ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
+ ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
+ ir_node * st;
+
+ /* mov ecx,<env> */
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, one, mode);
+ st = new_r_Store(block, mem, p, env, cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, four, mode);
+ /* jmp <callee> */
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
+ p = new_r_Add(block, p, one, mode);
+ st = new_r_Store(block, mem, p, callee, cons_none);
+ mem = new_r_Proj(st, mode_M, pn_Store_M);
- /* emit now all global declarations */
- be_gas_emit_decls(isa->base.main_env);
+ return mem;
+}
- pmap_destroy(isa->tv_ent);
- pmap_destroy(isa->types);
+static const ir_settings_arch_dep_t ia32_arch_dep = {
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 63, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
- be_emit_exit();
+ 1, /* allow Mulhs */
+ 1, /* allow Mulus */
+ 32, /* Mulh allowed up to 32 bit */
+};
+static backend_params ia32_backend_params = {
+ 1, /* support inline assembly */
+ 1, /* support Rotl nodes */
+ 0, /* little endian */
+ 1, /* modulo shift efficient */
+ 0, /* non-modulo shift not efficient */
+ &ia32_arch_dep, /* will be set later */
+ ia32_is_mux_allowed,
+ 32, /* machine_size */
+ NULL, /* float arithmetic mode, will be set below */
+ NULL, /* long long type */
+ NULL, /* unsigned long long type */
+ NULL, /* long double type */
+ 12, /* size of trampoline code */
+ 4, /* alignment of trampoline code */
+ ia32_create_trampoline_fkt,
+ 4 /* alignment of stack parameter */
+};
- free(self);
+/**
+ * Initializes the backend ISA.
+ */
+static void ia32_init(void)
+{
+ ir_mode *mode_long_long;
+ ir_mode *mode_unsigned_long_long;
+ ir_type *type_long_long;
+ ir_type *type_unsigned_long_long;
+
+ ia32_setup_cg_config();
+
+ init_asm_constraints();
+
+ ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
+
+ /* note mantissa is 64bit but with explicitely encoded 1 so the really
+ * usable part as counted by firm is only 63 bits */
+ ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
+ ia32_type_E = new_type_primitive(ia32_mode_E);
+ set_type_size_bytes(ia32_type_E, 12);
+ set_type_alignment_bytes(ia32_type_E, 4);
+
+ mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
+ type_long_long = new_type_primitive(mode_long_long);
+ mode_unsigned_long_long
+ = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
+ type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
+
+ ia32_backend_params.type_long_long = type_long_long;
+ ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
+
+ if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
+ ia32_backend_params.mode_float_arithmetic = NULL;
+ ia32_backend_params.type_long_double = NULL;
+ } else {
+ ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
+ ia32_backend_params.type_long_double = ia32_type_E;
+ }
+
+ ia32_register_init();
+ obstack_init(&opcodes_obst);
+ ia32_create_opcodes(&ia32_irn_ops);
}
+static void ia32_finish(void)
+{
+ if (between_type != NULL) {
+ free_type(between_type);
+ between_type = NULL;
+ }
+ ia32_free_opcodes();
+ obstack_free(&opcodes_obst, NULL);
+}
/**
- * Get the register class which shall be used to store a value of a given mode.
- * @param self The this pointer.
- * @param mode The mode in question.
- * @return A register class which can hold values of the given mode.
+ * The template that generates a new ISA object.
+ * Note that this template can be changed by command line
+ * arguments.
*/
-static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
+static ia32_isa_t ia32_isa_template = {
+ {
+ &ia32_isa_if, /* isa interface implementation */
+ N_IA32_REGISTERS,
+ ia32_registers,
+ N_IA32_CLASSES,
+ ia32_reg_classes,
+ &ia32_registers[REG_ESP], /* stack pointer register */
+ &ia32_registers[REG_EBP], /* base pointer register */
+ 2, /* power of two stack alignment, 2^2 == 4 */
+ 7, /* costs for a spill instruction */
+ 5, /* costs for a reload instruction */
+ false, /* no custom abi handling */
+ },
+ NULL, /* tv_ents */
+ IA32_FPU_ARCH_X87, /* FPU architecture */
+};
+
+static arch_env_t *ia32_begin_codegeneration(void)
{
- if (mode_is_float(mode)) {
- return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
- }
- else
- return &ia32_reg_classes[CLASS_ia32_gp];
+ ia32_isa_t *isa = XMALLOC(ia32_isa_t);
+
+ set_tarval_output_modes();
+
+ *isa = ia32_isa_template;
+ isa->tv_ent = pmap_create();
+
+ return &isa->base;
+}
+
+/**
+ * Closes the output file and frees the ISA structure.
+ */
+static void ia32_end_codegeneration(void *self)
+{
+ ia32_isa_t *isa = (ia32_isa_t*)self;
+ pmap_destroy(isa->tv_ent);
+ free(self);
}
/**
/**
* Get the ABI restrictions for procedure calls.
- * @param self The this pointer.
- * @param method_type The type of the method (procedure) in question.
- * @param abi The abi object to be modified
*/
-static void ia32_get_call_abi(const void *self, ir_type *method_type,
- be_abi_call_t *abi)
+static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
{
- ir_type *tp;
- ir_mode *mode;
unsigned cc;
int n, i, regnum;
int pop_amount = 0;
be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
- (void) self;
-
/* set abi flags for calls */
- call_flags.bits.left_to_right = 0; /* always last arg first on stack */
- call_flags.bits.store_args_sequential = 0;
- /* call_flags.bits.try_omit_fp not changed: can handle both settings */
- call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
- call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
+ /* call_flags.try_omit_fp not changed: can handle both settings */
+ call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
/* set parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
n = get_method_n_params(method_type);
for (i = regnum = 0; i < n; i++) {
- ir_mode *mode;
- const arch_register_t *reg = NULL;
+ const arch_register_t *reg = NULL;
+ ir_type *tp = get_method_param_type(method_type, i);
+ ir_mode *mode = get_type_mode(tp);
- tp = get_method_param_type(method_type, i);
- mode = get_type_mode(tp);
if (mode != NULL) {
reg = ia32_get_RegParam_reg(cc, regnum, mode);
}
/* In case of 64bit returns, we will have two 32bit values */
if (n == 2) {
- tp = get_method_res_type(method_type, 0);
- mode = get_type_mode(tp);
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
assert(!mode_is_float(mode) && "two FP results not supported");
be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
}
else if (n == 1) {
+ ir_type *tp = get_method_res_type(method_type, 0);
+ ir_mode *mode = get_type_mode(tp);
const arch_register_t *reg;
-
- tp = get_method_res_type(method_type, 0);
assert(is_atomic_type(tp));
- mode = get_type_mode(tp);
- reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
}
}
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
-{
- ir_mode *mode = arch_register_class_mode(cls);
- int bytes = get_mode_size_bytes(mode);
-
- if (mode_is_float(mode) && bytes > 8)
- return 16;
- return bytes;
-}
-
-/**
- * Return irp irgs in the desired order.
- */
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
-{
- (void) self;
- (void) irg_list;
- return NULL;
-}
-
static void ia32_mark_remat(ir_node *node)
{
if (is_ia32_irn(node)) {
}
}
-/**
- * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
- */
-static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
- ir_node *mux_false)
-{
- ir_node *cmp_l;
- ir_node *cmp_r;
- ir_relation relation;
-
- if (!is_Cmp(sel))
- return false;
-
- cmp_l = get_Cmp_left(sel);
- cmp_r = get_Cmp_right(sel);
- if (!mode_is_float(get_irn_mode(cmp_l)))
- return false;
-
- /* check for min/max. They're defined as (C-Semantik):
- * min(a, b) = a < b ? a : b
- * or min(a, b) = a <= b ? a : b
- * max(a, b) = a > b ? a : b
- * or max(a, b) = a >= b ? a : b
- * (Note we only handle float min/max here)
- */
- relation = get_Cmp_relation(sel);
- switch (relation) {
- case ir_relation_greater_equal:
- case ir_relation_greater:
- /* this is a max */
- if (cmp_l == mux_true && cmp_r == mux_false)
- return true;
- break;
- case ir_relation_less_equal:
- case ir_relation_less:
- /* this is a min */
- if (cmp_l == mux_true && cmp_r == mux_false)
- return true;
- break;
- case ir_relation_unordered_greater_equal:
- case ir_relation_unordered_greater:
- /* this is a min */
- if (cmp_l == mux_false && cmp_r == mux_true)
- return true;
- break;
- case ir_relation_unordered_less_equal:
- case ir_relation_unordered_less:
- /* this is a max */
- if (cmp_l == mux_false && cmp_r == mux_true)
- return true;
- break;
-
- default:
- break;
- }
-
- return false;
-}
-
-static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
-{
- ir_mode *mode = get_irn_mode(mux_true);
- (void) sel;
-
- if (!mode_is_int(mode) && !mode_is_reference(mode)
- && mode != mode_b)
- return false;
-
- if (is_Const(mux_true) && is_Const(mux_false)) {
- /* we can create a set plus up two 3 instructions for any combination
- * of constants */
- return true;
- }
-
- return false;
-}
-
-static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
- ir_node *mux_false)
-{
- (void) sel;
-
- if (!mode_is_float(get_irn_mode(mux_true)))
- return false;
-
- return is_Const(mux_true) && is_Const(mux_false);
-}
-
-static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
-{
- ir_node *cmp_left;
- ir_node *cmp_right;
- ir_node *sub_left;
- ir_node *sub_right;
- ir_mode *mode;
- ir_relation relation;
-
- if (!is_Cmp(sel))
- return false;
-
- mode = get_irn_mode(mux_true);
- if (mode_is_signed(mode) || mode_is_float(mode))
- return false;
-
- relation = get_Cmp_relation(sel);
- cmp_left = get_Cmp_left(sel);
- cmp_right = get_Cmp_right(sel);
-
- /* "move" zero constant to false input */
- if (is_Const(mux_true) && is_Const_null(mux_true)) {
- ir_node *tmp = mux_false;
- mux_false = mux_true;
- mux_true = tmp;
- relation = get_negated_relation(relation);
- }
- if (!is_Const(mux_false) || !is_Const_null(mux_false))
- return false;
- if (!is_Sub(mux_true))
- return false;
- sub_left = get_Sub_left(mux_true);
- sub_right = get_Sub_right(mux_true);
-
- /* Mux(a >=u b, 0, a-b) */
- if ((relation & ir_relation_greater)
- && sub_left == cmp_left && sub_right == cmp_right)
- return true;
- /* Mux(a <=u b, 0, b-a) */
- if ((relation & ir_relation_less)
- && sub_left == cmp_right && sub_right == cmp_left)
- return true;
-
- return false;
-}
-
-static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
- ir_node *mux_true)
-{
- ir_mode *mode;
-
- /* we can handle Set for all modes and compares */
- if (mux_is_set(sel, mux_true, mux_false))
- return true;
- /* SSE has own min/max operations */
- if (ia32_cg_config.use_sse2
- && mux_is_float_min_max(sel, mux_true, mux_false))
- return true;
- /* we can handle Mux(?, Const[f], Const[f]) */
- if (mux_is_float_const_const(sel, mux_true, mux_false)) {
-#ifdef FIRM_GRGEN_BE
- /* well, some code selectors can't handle it */
- if (be_transformer != TRANSFORMER_PBQP
- || be_transformer != TRANSFORMER_RAND)
- return true;
-#else
- return true;
-#endif
- }
-
- /* no support for 64bit inputs to cmov */
- mode = get_irn_mode(mux_true);
- if (get_mode_size_bits(mode) > 32)
- return false;
- /* we can handle Abs for all modes and compares (except 64bit) */
- if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
- return true;
- /* we can't handle MuxF yet */
- if (mode_is_float(mode))
- return false;
-
- if (mux_is_doz(sel, mux_true, mux_false))
- return true;
-
- /* Check Cmp before the node */
- if (is_Cmp(sel)) {
- ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
-
- /* we can't handle 64bit compares */
- if (get_mode_size_bits(cmp_mode) > 32)
- return false;
-
- /* we can't handle float compares */
- if (mode_is_float(cmp_mode))
- return false;
- }
-
- /* did we disable cmov generation? */
- if (!ia32_cg_config.use_cmov)
- return false;
-
- /* we can use a cmov */
- return true;
-}
-
static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
{
(void) c;
return ia32_get_clobber_register(clobber) != NULL;
}
-static ir_node *ia32_create_set(ir_node *cond)
-{
- /* ia32-set function produces 8-bit results which have to be converted */
- ir_node *set = ir_create_mux_set(cond, mode_Bu);
- ir_node *block = get_nodes_block(set);
- return new_r_Conv(block, set, mode_Iu);
-}
-
static void ia32_lower_for_target(void)
{
+ ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
size_t i, n_irgs = get_irp_n_irgs();
- lower_mode_b_config_t lower_mode_b_config = {
- mode_Iu, /* lowered mode */
- ia32_create_set,
- 0, /* don't lower direct compares */
- };
- lower_params_t params = {
- 4, /* def_ptr_alignment */
- LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
- ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
- NULL, /* find pointer type */
- NULL, /* ret_compound_in_regs */
- };
/* perform doubleword lowering */
lwrdw_param_t lower_dw_params = {
&intrinsic_env,
};
- /* lower compound param handling */
- lower_calls_with_compounds(¶ms);
+ /* lower compound param handling
+ * Note: we lower compound arguments ourself, since on ia32 we don't
+ * have hidden parameters but know where to find the structs on the stack.
+ * (This also forces us to always allocate space for the compound arguments
+ * on the callframe and we can't just use an arbitrary position on the
+ * stackframe)
+ */
+ lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
- lower_dw_ops(&lower_dw_params);
+ /* replace floating point operations by function calls */
+ if (ia32_cg_config.use_softfloat) {
+ lower_floating_point();
+ }
for (i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
- /* lower for mode_b stuff */
- ir_lower_mode_b(irg, &lower_mode_b_config);
/* break up switches with wide ranges */
- lower_switch(irg, 256, true);
+ lower_switch(irg, 4, 256, mode_gp);
}
-}
-/**
- * Create the trampoline code.
- */
-static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
-{
- ir_graph *irg = get_irn_irg(block);
- ir_node *p = trampoline;
- ir_mode *mode = get_irn_mode(p);
- ir_node *st;
+ ir_prepare_dw_lowering(&lower_dw_params);
+ ir_lower_dw_ops();
- /* mov ecx,<env> */
- st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
- mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, env, cons_none);
- mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
- /* jmp <callee> */
- st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
- mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, callee, cons_none);
- mem = new_r_Proj(st, mode_M, pn_Store_M);
- p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* lower for mode_b stuff */
+ ir_lower_mode_b(irg, mode_Iu);
+ }
- return mem;
+ for (i = 0; i < n_irgs; ++i) {
+ ir_graph *irg = get_irp_irg(i);
+ /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
+ * so we can generate rep movs later, and turn all big CopyBs into
+ * memcpy calls. */
+ lower_CopyB(irg, 64, 8193, true);
+ }
}
/**
*/
static const backend_params *ia32_get_libfirm_params(void)
{
- static const ir_settings_arch_dep_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 63, /* maximum shift amount */
- ia32_evaluate_insn, /* evaluate the instruction sequence */
-
- 1, /* allow Mulhs */
- 1, /* allow Mulus */
- 32, /* Mulh allowed up to 32 bit */
- };
- static backend_params p = {
- 1, /* support inline assembly */
- 1, /* support Rotl nodes */
- 0, /* little endian */
- NULL, /* will be set later */
- ia32_is_mux_allowed,
- NULL, /* float arithmetic mode, will be set below */
- 12, /* size of trampoline code */
- 4, /* alignment of trampoline code */
- ia32_create_trampoline_fkt,
- 4 /* alignment of stack parameter */
- };
-
- ia32_setup_cg_config();
-
- /* doesn't really belong here, but this is the earliest place the backend
- * is called... */
- init_asm_constraints();
+ return &ia32_backend_params;
+}
- p.dep_param = &ad;
- if (! ia32_cg_config.use_sse2)
- p.mode_float_arithmetic = mode_E;
- return &p;
+/**
+ * Check if the given register is callee or caller save.
+ */
+static int ia32_register_saved_by(const arch_register_t *reg, int callee)
+{
+ if (callee) {
+ /* check for callee saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EBX:
+ case REG_GP_ESI:
+ case REG_GP_EDI:
+ case REG_GP_EBP:
+ return 1;
+ default:
+ return 0;
+ }
+ }
+ } else {
+ /* check for caller saved */
+ if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
+ switch (reg->index) {
+ case REG_GP_EDX:
+ case REG_GP_ECX:
+ case REG_GP_EAX:
+ return 1;
+ default:
+ return 0;
+ }
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
+ /* all XMM registers are caller save */
+ return reg->index != REG_XMM_NOREG;
+ } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
+ /* all FP registers are caller save */
+ return reg->index != REG_FP_NOREG;
+ }
+ }
+ return 0;
}
static const lc_opt_enum_int_items_t gas_items[] = {
const arch_isa_if_t ia32_isa_if = {
ia32_init,
- ia32_lower_for_target,
- ia32_done,
- ia32_handle_intrinsics,
- ia32_get_reg_class_for_mode,
- ia32_get_call_abi,
- ia32_get_reg_class_alignment,
+ ia32_finish,
ia32_get_libfirm_params,
- ia32_get_irg_list,
- ia32_mark_remat,
+ ia32_lower_for_target,
ia32_parse_asm_constraint,
ia32_is_valid_clobber,
+ ia32_begin_codegeneration,
+ ia32_end_codegeneration,
ia32_init_graph,
+ ia32_get_call_abi,
+ ia32_mark_remat,
ia32_get_pic_base, /* return node used as base in pic code addresses */
+ be_new_spill,
+ be_new_reload,
+ ia32_register_saved_by,
+
+ ia32_handle_intrinsics,
ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
ia32_before_ra, /* before register allocation hook */
- ia32_after_ra, /* after register allocation hook */
- ia32_finish, /* called before codegen */
+ ia32_finish_graph, /* called before codegen */
ia32_emit, /* emit && done */
};
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
-
ia32_init_emitter();
ia32_init_finish();
ia32_init_optimize();
projects / libfirm / blobdiff