#include "ia32_map_regs.h"
#include "ia32_optimize.h"
#include "ia32_x87.h"
+#include "ia32_dbg_stat.h"
#define DEBUG_MODULE "firm.be.ia32.isa"
}
}
else {
- /* treat Phi like Const with default requirements */
- if (is_Phi(irn)) {
- DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
+ /* treat Unknowns like Const with default requirements */
+ if (is_Unknown(irn)) {
+ DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
if (mode_is_float(mode)) {
if (USE_SSE2(ops->cg))
- memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
else
- memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
}
else if (mode_is_int(mode) || mode_is_reference(mode))
- memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
+ memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
+ DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
return NULL;
}
else
- assert(0 && "unsupported Phi-Mode");
+ assert(0 && "unsupported Unknown-Mode");
}
else {
DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
irn = my_skip_proj(irn);
if (is_cfop(irn))
return arch_irn_class_branch;
+ else if (is_ia32_Cnst(irn))
+ return arch_irn_class_const;
else if (is_ia32_irn(irn))
return arch_irn_class_normal;
else
if (is_ia32_irn(irn))
return get_ia32_flags(irn);
else {
+ if (is_Unknown(irn))
+ return arch_irn_flags_ignore;
return 0;
}
}
typedef struct {
be_abi_call_flags_bits_t flags;
const arch_isa_t *isa;
+ const arch_env_t *aenv;
ir_graph *irg;
} ia32_abi_env_t;
be_abi_call_flags_t fl = be_abi_call_get_flags(call);
env->flags = fl.bits;
env->irg = irg;
+ env->aenv = aenv;
env->isa = aenv->isa;
return env;
}
pset_insert_ptr(s, env->isa->bp);
}
+/**
+ * Generate the routine prologue.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
+ */
static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
{
ia32_abi_env_t *env = self;
- const arch_register_t *frame_reg = env->isa->sp;
- if(!env->flags.try_omit_fp) {
+ if (!env->flags.try_omit_fp) {
int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
ir_node *bl = get_irg_start_block(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
- ir_node *store_bp;
-
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
- store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
- set_ia32_am_support(store_bp, ia32_am_Dest);
- set_ia32_am_flavour(store_bp, ia32_B);
- set_ia32_op_type(store_bp, ia32_AddrModeD);
- *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
+ ir_node *push;
+
+ /* push ebp */
+ push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
+ curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
+ *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
+
+ /* the push must have SP out register */
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ set_ia32_flags(push, arch_irn_flags_ignore);
+
+ /* move esp to ebp */
curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
+ arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
+ /* beware: the copy must be done before any other sp use */
+ curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
+ be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
+
be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+
+ return env->isa->bp;
}
- return frame_reg;
+ return env->isa->sp;
}
+/**
+ * Generate the routine epilogue.
+ * @param self The callback object.
+ * @param mem A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @return The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
+ */
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = self;
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
- if(env->flags.try_omit_fp) {
+ if (env->flags.try_omit_fp) {
+ /* simply remove the stack frame here */
curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
}
-
else {
- ir_node *load_bp;
+ const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+ int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
+
+ /* AMD processors prefer leave at the end of a routine */
+ if (ARCH_AMD(isa->opt_arch)) {
+ ir_node *leave;
+
+ /* leave */
+ leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
+ set_ia32_flags(leave, arch_irn_flags_ignore);
+ curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
+ curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+ *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
+ }
+ else {
+ ir_node *pop;
+
+ /* copy ebp to esp */
+ curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
- curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
- load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
- set_ia32_am_support(load_bp, ia32_am_Source);
- set_ia32_am_flavour(load_bp, ia32_B);
- set_ia32_op_type(load_bp, ia32_AddrModeS);
- set_ia32_ls_mode(load_bp, mode_bp);
- curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
- *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
+ /* pop ebp */
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
+ set_ia32_flags(pop, arch_irn_flags_ignore);
+ curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
+ curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+ *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
+ }
+ arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+ arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
}
be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
+ ia32_register_transformers();
irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
- DEBUG_ONLY(cg->mod = old_mod;)
-
- if (cg->opt.doam) {
+ if (cg->opt & IA32_OPT_DOAM) {
edges_deactivate(cg->irg);
//dead_node_elimination(cg->irg);
edges_activate(cg->irg);
+ FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
+
irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
}
+
+ DEBUG_ONLY(cg->mod = old_mod;)
}
* is not fulfilled.
* Transform Sub into Neg -- Add if IN2 == OUT
*/
-static void ia32_finish_irg_walker(ir_node *irn, void *env) {
+static void ia32_finish_node(ir_node *irn, void *env) {
ia32_code_gen_t *cg = env;
const ia32_register_req_t **reqs;
const arch_register_t *out_reg, *in_reg, *in2_reg;
/* AM Dest nodes don't produce any values */
op_tp = get_ia32_op_type(irn);
if (op_tp == ia32_AddrModeD)
- return;
+ goto end;
reqs = get_ia32_out_req_all(irn);
n_res = get_ia32_n_res(irn);
block = get_nodes_block(irn);
/* check all OUT requirements, if there is a should_be_same */
- if (op_tp == ia32_Normal) {
+ if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) &&
+ ! is_ia32_Lea(irn) && ! is_ia32_Conv_I2I(irn) && ! is_ia32_Conv_I2I8Bit(irn))
+ {
for (i = 0; i < n_res; i++) {
if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
/* get in and out register */
out_reg = get_ia32_out_reg(irn, i);
in_node = get_irn_n(irn, reqs[i]->same_pos);
in_reg = arch_get_irn_register(cg->arch_env, in_node);
- in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
/* don't copy ignore nodes */
if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
/* check if in and out register are equal */
if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
/* in case of a commutative op: just exchange the in's */
- if (is_ia32_commutative(irn) && REGS_ARE_EQUAL(out_reg, in2_reg)) {
- set_irn_n(irn, reqs[i]->same_pos, in2_node);
- set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
+ /* beware: the current op could be everything, so test for ia32 */
+ /* commutativity first before getting the second in */
+ if (is_ia32_commutative(irn)) {
+ in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
+ in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
+
+ if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
+ set_irn_n(irn, reqs[i]->same_pos, in2_node);
+ set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
+ }
+ else
+ goto insert_copy;
}
else {
+insert_copy:
DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
/* create copy from in register */
copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
+ DBG_OPT_2ADDRCPY(copy);
+
/* destination is the out register */
arch_set_irn_register(cg->arch_env, copy, out_reg);
/* to change it, as CMP doesn't support immediate as */
/* left operands. */
if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
- long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
set_ia32_op_type(irn, ia32_AddrModeD);
- set_ia32_pncode(irn, pnc);
+ set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
}
/* check if there is a sub which need to be transformed */
/* transform a LEA into an Add if possible */
ia32_transform_lea_to_add(irn, cg);
}
+end:
/* check for peephole optimization */
ia32_peephole_optimization(irn, cg);
}
+static void ia32_finish_irg_walker(ir_node *block, void *env) {
+ ir_node *irn, *next;
+
+ for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
+ next = sched_next(irn);
+ ia32_finish_node(irn, env);
+ }
+}
+
/**
* Add Copy nodes for not fulfilled should_be_equal constraints
*/
static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
- irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
+ irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
}
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
+ DBG_OPT_RELOAD2LD(irn, new_op);
+
proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
if (sched_point) {
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
else
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
+ DBG_OPT_SPILL2ST(irn, new_op);
+
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
if (sched_point) {
sched_add_after(sched_point, new_op);
cg->isa = isa;
cg->birg = birg;
cg->blk_sched = NULL;
+ cg->fp_to_gp = NULL;
+ cg->gp_to_fp = NULL;
cg->fp_kind = isa->fp_kind;
cg->used_fp = fp_none;
FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
- /* set optimizations */
- cg->opt.incdec = 0;
- cg->opt.doam = 1;
- cg->opt.placecnst = 1;
- cg->opt.immops = 1;
- cg->opt.extbb = 1;
+ /* copy optimizations from isa for easier access */
+ cg->opt = isa->opt;
/* enter it */
isa->cg = cg;
}
#endif /* NDEBUG */
- isa->num_codegens++;
-
- if (isa->num_codegens > 1)
- cg->emit_decls = 0;
- else
- cg->emit_decls = 1;
-
cur_reg_set = cg->reg_set;
ia32_irn_ops.cg = cg;
* arguments.
*/
static ia32_isa_t ia32_isa_template = {
- &ia32_isa_if, /* isa interface implementation */
- &ia32_gp_regs[REG_ESP], /* stack pointer register */
- &ia32_gp_regs[REG_EBP], /* base pointer register */
- -1, /* stack direction */
- 0, /* number of code generator objects so far */
+ {
+ &ia32_isa_if, /* isa interface implementation */
+ &ia32_gp_regs[REG_ESP], /* stack pointer register */
+ &ia32_gp_regs[REG_EBP], /* base pointer register */
+ -1, /* stack direction */
+ },
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* types */
NULL, /* tv_ents */
+ (0 |
+ IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
+ IA32_OPT_DOAM | /* optimize address mode default: on */
+ IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
+ IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
+ IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
arch_pentium_4, /* instruction architecture */
arch_pentium_4, /* optimize for architecture */
fp_sse2, /* use sse2 unit */
ia32_create_opcodes();
ia32_register_copy_attr_func();
+ if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
+ (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
+ /* no SSE2 for these cpu's */
+ isa->fp_kind = fp_x87;
+
+ if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
+ /* Pentium 4 don't like inc and dec instructions */
+ isa->opt &= ~IA32_OPT_INCDEC;
+ }
+
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
isa->types = pmap_create();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
- /* patch regigter names of x87 registers */
+ /* patch register names of x87 registers */
if (USE_x87(isa)) {
ia32_st_regs[0].name = "st";
ia32_st_regs[1].name = "st(1)";
isa->name_obst_size = 0;
#endif /* NDEBUG */
- fprintf(isa->out, "\t.intel_syntax\n");
+ fprintf(isa->out, "\t.intel_syntax\n");
inited = 1;
int i, ignore_1, ignore_2;
ir_mode **modes;
const arch_register_t *reg;
- be_abi_call_flags_t call_flags;
+ be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
/* set abi flags for calls */
- call_flags.bits.left_to_right = 0;
- call_flags.bits.store_args_sequential = 0;
- call_flags.bits.try_omit_fp = 1;
- call_flags.bits.fp_free = 0;
- call_flags.bits.call_has_imm = 1;
+ call_flags.bits.left_to_right = 0; /* always last arg first on stack */
+ call_flags.bits.store_args_sequential = 0; /* use stores instead of push */
+ /* call_flags.bits.try_omit_fp not changed: can handle both settings */
+ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
+ call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
/* set stack parameter passing style */
be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
{ "pentiumpro", arch_pentium_pro, },
{ "686", arch_pentium_pro, },
{ "pentiummmx", arch_pentium_mmx, },
- { "pentiummmx", arch_pentium_mmx, },
{ "pentium2", arch_pentium_2, },
{ "p2", arch_pentium_2, },
{ "pentium3", arch_pentium_3, },
LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
+ LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
+ LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
+ LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
+ LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
{ NULL }
};
* ia32-arch=arch create instruction for arch
* ia32-opt=arch optimize for run on arch
* ia32-fpunit=unit select floating point unit (x87 or SSE2)
+ * ia32-incdec optimize for inc/dec
+ * ia32-noaddrmode do not use address mode
+ * ia32-noplacecnst do not place constants,
+ * ia32-noimmop no operations with immediates
+ * ia32-noextbb do not use extended basic block scheduling
*/
static void ia32_register_options(lc_opt_entry_t *ent)
{
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