char buf[64];
const ia32_irn_ops_t *ops = self;
- if (is_ia32_use_frame(irn)) {
+ if (is_ia32_use_frame(irn) && bias != 0) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
dump_ir_block_graph_sched(cg->irg, "-transformed");
edges_deactivate(cg->irg);
edges_activate(cg->irg);
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
- dump_ir_block_graph_sched(cg->irg, "-am");
+
+ if (cg->opt.doam) {
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
+ dump_ir_block_graph_sched(cg->irg, "-am");
+ }
}
if (! is_ia32_irn(irn))
return;
+ /* nodes with destination address mode don't produce values */
+ if (get_ia32_op_type(irn) == ia32_AddrModeD)
+ return;
+
reqs = get_ia32_out_req_all(irn);
n_res = get_ia32_n_res(irn);
block = get_nodes_block(irn);
/* insert copy before the node into the schedule */
sched_add_before(irn, copy);
+
+ /* set copy as in */
+ set_irn_n(irn, reqs[i]->same_pos, copy);
}
}
}
* Transforms a be node into a Load.
*/
static void transform_to_Load(ia32_transform_env_t *env) {
- ir_node *irn = env->irn;
- entity *ent = be_get_frame_entity(irn);
- ir_mode *mode = env->mode;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_rd_NoMem(env->irg);
- ir_node *new_op, *proj;
+ ir_node *irn = env->irn;
+ entity *ent = be_get_frame_entity(irn);
+ ir_mode *mode = env->mode;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
ir_node *sched_point = NULL;
+ ir_node *ptr = get_irn_n(irn, 0);
+ ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
+ ir_node *new_op, *proj;
const arch_register_t *reg;
if (sched_is_scheduled(irn)) {
}
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_irn_n(irn, 0), noreg, nomem, mode_T);
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_irn_n(irn, 0), noreg, nomem, mode_T);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
set_ia32_am_support(new_op, ia32_am_Source);
/* copy the register from the old node to the new Load */
reg = arch_get_irn_register(env->cg->arch_env, irn);
- arch_set_irn_register(env->cg->arch_env, irn, reg);
+ arch_set_irn_register(env->cg->arch_env, new_op, reg);
exchange(irn, proj);
cg->tv_ent = pmap_create();
cg->birg = birg;
+ /* set optimizations */
+ cg->opt.incdec = 0;
+ cg->opt.doam = 1;
+ cg->opt.placecnst = 1;
+ cg->opt.immops = 1;
+
isa->num_codegens++;
if (isa->num_codegens > 1)