#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
+#include "../be.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
- if (! cg->noreg_gp) {
- cg->noreg_gp = be_new_NoReg(&ia32_gp_regs[REG_XXX], cg->irg, get_irg_start_block(cg->irg));
- }
-
- return cg->noreg_gp;
+ return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
}
ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
- if (! cg->noreg_fp) {
- cg->noreg_fp = be_new_NoReg(&ia32_fp_regs[REG_XXXX], cg->irg, get_irg_start_block(cg->irg));
- }
-
- return cg->noreg_fp;
+ return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
}
/**************************************************
return (ir_node *)n;
}
-static int is_Call_Proj(const ir_node *n) {
- if (is_Proj(n) &&
- is_Proj(get_Proj_pred(n)) &&
- get_irn_mode(get_Proj_pred(n)) == mode_T &&
- is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
- {
- return 1;
- }
-
- return 0;
-}
-
-static int is_Start_Proj(const ir_node *n) {
- if (is_Proj(n) &&
- is_Proj(get_Proj_pred(n)) &&
- get_irn_mode(get_Proj_pred(n)) == mode_T &&
- is_Start(get_Proj_pred(get_Proj_pred(n))))
- {
- return 1;
- }
-
- return 0;
-}
-
-static int is_P_frame_base_Proj(const ir_node *n) {
- if (is_Proj(n) &&
- is_Start(get_Proj_pred(n)) &&
- get_Proj_proj(n) == pn_Start_P_frame_base)
- {
- return 1;
- }
-
- return 0;
-}
-
-static int is_used_by_Keep(const ir_node *n) {
- return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
-}
-
/**
* Return register requirements for an ia32 node.
* If the node returns a tuple (mode_T) then the proj's
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
- if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
- if (pos >= 0) {
- req = NULL;
- }
- else {
- irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
- memcpy(req, &(irn_req->req), sizeof(*req));
- }
-
- return req;
- }
- else if (is_Start_Proj(irn)) {
- irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
- assert(irn_req && "missing requirement for regparam");
- memcpy(req, &(irn_req->req), sizeof(*req));
- return req;
- //return NULL;
- }
- else if (is_Proj(irn)) {
+ if (is_Proj(irn)) {
if (pos == -1) {
node_pos = ia32_translate_proj_pos(irn);
}
else
assert(0 && "unsupported Phi-Mode");
}
- else if (is_Start(irn)) {
- DB((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
- switch (node_pos) {
- case pn_Start_X_initial_exec:
- case pn_Start_P_value_arg_base:
- case pn_Start_P_globals:
- case pn_Start_P_frame_base:
- memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
- break;
- case pn_Start_T_args:
- assert(0 && "ProjT(pn_Start_T_args) should not be asked");
- }
- }
- else if (get_irn_op(irn) == op_Return && pos > 0) {
- DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
- memcpy(req, &(ia32_default_req_ia32_gp_eax.req), sizeof(*req));
- }
else {
DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
req = NULL;
irn = my_skip_proj(irn);
if (is_cfop(irn))
return arch_irn_class_branch;
- else if (is_ia32_Call(irn))
- return arch_irn_class_call;
else if (is_ia32_irn(irn))
return arch_irn_class_normal;
else
}
}
+static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
+ return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
+}
+
+static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
+ char buf[64];
+ const ia32_irn_ops_t *ops = self;
+
+ if (is_ia32_use_frame(irn) && bias != 0) {
+ ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
+
+ DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
+ snprintf(buf, sizeof(buf), "%d", bias);
+ add_ia32_am_offs(irn, buf);
+ am_flav |= ia32_O;
+ set_ia32_am_flavour(irn, am_flav);
+ }
+}
+
/* fill register allocator interface */
static const arch_irn_ops_if_t ia32_irn_ops_if = {
ia32_set_irn_reg,
ia32_get_irn_reg,
ia32_classify,
- ia32_get_flags
+ ia32_get_flags,
+ ia32_get_frame_entity,
+ ia32_set_stack_bias
};
ia32_irn_ops_t ia32_irn_ops = {
dump_ir_block_graph_sched(cg->irg, "-transformed");
edges_deactivate(cg->irg);
edges_activate(cg->irg);
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
- dump_ir_block_graph_sched(cg->irg, "-am");
-}
+ if (cg->opt.doam) {
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
+ dump_ir_block_graph_sched(cg->irg, "-am");
+ }
+}
/**
- * Stack reservation and StackParam lowering.
+ * Insert copies for all ia32 nodes where the should_be_same requirement
+ * is not fulfilled.
*/
-static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
-#if 0
- firm_dbg_module_t *mod = cg->mod;
- ir_node *frame = get_irg_frame(irg);
- ir_node *end_block = get_irg_end_block(irg);
- ir_node **returns, **in, **new_in;
- ir_node *stack_reserve, *sched_point;
- ir_node *stack_free, *new_ret, *return_block;
- int stack_size = 0, i, n_arg;
- arch_register_t *stack_reg;
- tarval *stack_size_tv;
- dbg_info *frame_dbg;
-
- /* Determine stack register */
- if (cg->has_alloca) {
- stack_reg = &ia32_gp_regs[REG_EBP];
- }
- else {
- stack_reg = &ia32_gp_regs[REG_ESP];
- }
-
- /* If frame is used, then we need to reserve some stackspace. */
- if (get_irn_n_edges(frame) > 0) {
- /* The initial stack reservation. */
- stack_size = get_type_size_bytes(get_irg_frame_type(irg));
- frame_dbg = get_irn_dbg_info(frame);
- stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
- stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
- set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
-
- assert(stack_size && "bOrken stack layout");
-
- /* reroute all edges from frame pointer to corrected frame pointer */
- edges_reroute(frame, stack_reserve, irg);
- set_irn_n(stack_reserve, 0, frame);
-
- /* schedule frame pointer */
- if (! sched_is_scheduled(frame)) {
- sched_add_after(get_irg_start(irg), frame);
- }
-
- /* set register */
- arch_set_irn_register(cg->arch_env, frame, stack_reg);
- arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
-
- /* insert into schedule */
- sched_add_after(frame, stack_reserve);
-
- /* Free stack for each Return node */
- returns = get_Block_cfgpred_arr(end_block);
- for (i = 0; i < get_Block_n_cfgpreds(end_block); i++) {
- assert(get_irn_opcode(returns[i]) == iro_Return && "cfgpred of endblock is not a return");
-
- return_block = get_nodes_block(returns[i]);
-
- /* free the stack */
- stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
- set_ia32_Immop_tarval(stack_free, stack_size_tv);
- arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
-
- DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
-
- /* get the old Return arguments */
- n_arg = get_Return_n_ress(returns[i]);
- in = get_Return_res_arr(returns[i]);
- new_in = alloca((n_arg + 2) * sizeof(new_in[0]));
-
- /* copy the old to the new in's */
- memcpy(new_in, in, n_arg * sizeof(in[0]));
- new_in[n_arg++] = stack_free;
- new_in[n_arg++] = get_Return_mem(returns[i]);
-
- /* create the new return node */
- new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
-
- /* In case the return node is the only node in the block, */
- /* it is not scheduled, so we need this work-around. */
- if (! sched_is_scheduled(returns[i])) {
- sched_point = return_block;
- }
- else {
- sched_point = sched_prev(returns[i]);
- sched_remove(returns[i]);
+static void ia32_finish_irg_walker(ir_node *irn, void *env) {
+ ia32_code_gen_t *cg = env;
+ const ia32_register_req_t **reqs;
+ const arch_register_t *out_reg, *in_reg;
+ int n_res, i;
+ ir_node *copy, *in_node, *block;
+
+ if (! is_ia32_irn(irn))
+ return;
+
+ /* nodes with destination address mode don't produce values */
+ if (get_ia32_op_type(irn) == ia32_AddrModeD)
+ return;
+
+ reqs = get_ia32_out_req_all(irn);
+ n_res = get_ia32_n_res(irn);
+ block = get_nodes_block(irn);
+
+ /* check all OUT requirements, if there is a should_be_same */
+ for (i = 0; i < n_res; i++) {
+ if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
+ /* get in and out register */
+ out_reg = get_ia32_out_reg(irn, i);
+ in_node = get_irn_n(irn, reqs[i]->same_pos);
+ in_reg = arch_get_irn_register(cg->arch_env, in_node);
+
+ /* check if in and out register are equal */
+ if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
+ DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
+
+ /* create copy from in register */
+ copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
+
+ /* destination is the out register */
+ arch_set_irn_register(cg->arch_env, copy, out_reg);
+
+ /* insert copy before the node into the schedule */
+ sched_add_before(irn, copy);
+
+ /* set copy as in */
+ set_irn_n(irn, reqs[i]->same_pos, copy);
}
-
- /* exchange the old return with the new one */
- exchange(returns[i], new_ret);
-
- DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
-
- /* remove the old one from schedule and add the new nodes properly */
- sched_add_after(sched_point, new_ret);
- sched_add_after(sched_point, stack_free);
}
}
-#endif
+}
+
+/**
+ * Add Copy nodes for not fulfilled should_be_equal constraints
+ */
+static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
+ irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
}
* Dummy functions for hooks we don't need but which must be filled.
*/
static void ia32_before_sched(void *self) {
- ia32_code_gen_t *cg = self;
-
- lower_nodes_before_sched(cg->irg, cg->arch_env);
}
static void ia32_before_ra(void *self) {
}
+
/**
- * Creates a Store for a Spill
+ * Transforms a be node into a Load.
*/
-static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
- ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- dbg_info *dbg = get_irn_dbg_info(spill);
- ir_node *block = get_nodes_block(spill);
- ir_node *ptr = get_irg_frame(irg);
- ir_node *val = be_get_Spill_context(spill);
- ir_node *mem = new_rd_NoMem(irg);
- ir_mode *mode = get_irn_mode(spill);
- entity *ent = be_get_spill_entity(spill);
- unsigned offs = get_entity_offset_bytes(ent);
- ir_node *noreg, *res;
- char buf[64];
-
- DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
+static void transform_to_Load(ia32_transform_env_t *env) {
+ ir_node *irn = env->irn;
+ entity *ent = be_get_frame_entity(irn);
+ ir_mode *mode = env->mode;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_node *sched_point = NULL;
+ ir_node *ptr = get_irn_n(irn, 0);
+ ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
+ ir_node *new_op, *proj;
+ const arch_register_t *reg;
+
+ if (sched_is_scheduled(irn)) {
+ sched_point = sched_prev(irn);
+ }
if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_fp(cg);
- res = new_rd_ia32_fStore(dbg, irg, block, ptr, noreg, val, mem, mode);
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
else {
- noreg = ia32_new_NoReg_gp(cg);
- res = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, mem, mode);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
- snprintf(buf, sizeof(buf), "%d", offs);
- add_ia32_am_offs(res, buf);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
+
+ if (sched_point) {
+ sched_add_after(sched_point, new_op);
+ sched_add_after(new_op, proj);
+
+ sched_remove(irn);
+ }
+
+ /* copy the register from the old node to the new Load */
+ reg = arch_get_irn_register(env->cg->arch_env, irn);
+ arch_set_irn_register(env->cg->arch_env, new_op, reg);
+
+ exchange(irn, proj);
- return res;
}
/**
- * Create a Load for a Spill
+ * Transforms a be node into a Store.
*/
-static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
- ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- dbg_info *dbg = get_irn_dbg_info(reload);
- ir_node *block = get_nodes_block(reload);
- ir_node *ptr = get_irg_frame(irg);
- ir_mode *mode = get_irn_mode(reload);
- ir_node *pred = get_irn_n(reload, 0);
- char buf[64];
- char *ofs;
- ir_node *noreg, *res;
-
- /* Get the offset to Load from. It can either be a Spill or a Store. */
- if (be_is_Spill(pred)) {
- entity *ent = be_get_spill_entity(pred);
- unsigned offs = get_entity_offset_bytes(ent);
- DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
-
- snprintf(buf, sizeof(buf), "%d", offs);
- }
- else if (is_ia32_Store(pred) || is_ia32_fStore(pred)) {
- ofs = get_ia32_am_offs(pred);
- strncpy(buf, ofs, sizeof(buf));
- free(ofs);
- }
- else {
- assert(0 && "unsupported Reload predecessor");
+static void transform_to_Store(ia32_transform_env_t *env) {
+ ir_node *irn = env->irn;
+ entity *ent = be_get_frame_entity(irn);
+ ir_mode *mode = env->mode;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_node *ptr = get_irn_n(irn, 0);
+ ir_node *val = get_irn_n(irn, 1);
+ ir_node *new_op, *proj;
+ ir_node *sched_point = NULL;
+
+ if (sched_is_scheduled(irn)) {
+ sched_point = sched_prev(irn);
}
- /* Create the Load */
if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_fp(cg);
- res = new_rd_ia32_fLoad(dbg, irg, block, ptr, noreg, pred, mode_T);
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
}
else {
- noreg = ia32_new_NoReg_gp(cg);
- res = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, pred, mode_T);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
}
- /* Set offset */
- add_ia32_am_offs(res, buf);
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
- /* Return the result Proj */
- return new_rd_Proj(dbg, irg, block, res, mode, 0);
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+
+ if (sched_point) {
+ sched_add_after(sched_point, new_op);
+ sched_add_after(new_op, proj);
+
+ sched_remove(irn);
+ }
+
+ exchange(irn, proj);
+
+}
+
+/**
+ * Calls the transform functions for StackParam, Spill and Reload.
+ */
+static void ia32_after_ra_walker(ir_node *node, void *env) {
+ ia32_code_gen_t *cg = env;
+ ir_node *new_node = NULL;
+ ia32_transform_env_t tenv;
+
+ if (is_Block(node))
+ return;
+
+ tenv.block = get_nodes_block(node);
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irg = current_ir_graph;
+ tenv.irn = node;
+ tenv.mod = cg->mod;
+ tenv.mode = get_irn_mode(node);
+ tenv.cg = cg;
+
+ if (be_is_StackParam(node) || be_is_Reload(node)) {
+ transform_to_Load(&tenv);
+ }
+ else if (be_is_Spill(node)) {
+ transform_to_Store(&tenv);
+ }
+}
+
+/**
+ * We transform StackParam, Spill and Reload here. This needs to be done before
+ * stack biasing otherwise we would miss the corrected offset for these nodes.
+ */
+static void ia32_after_ra(void *self) {
+ ia32_code_gen_t *cg = self;
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
}
+
/**
* Emits the code, closes the output file and frees
* the code generator interface.
*/
static void ia32_codegen(void *self) {
ia32_code_gen_t *cg = self;
- ir_graph *irg = cg->irg;
- FILE *out = cg->out;
+ ir_graph *irg = cg->irg;
+ FILE *out = cg->out;
if (cg->emit_decls) {
ia32_gen_decls(cg->out);
}
ia32_finish_irg(irg, cg);
- //dump_ir_block_graph_sched(irg, "-finished");
+ dump_ir_block_graph_sched(irg, "-finished");
ia32_gen_routine(out, irg, cg);
cur_reg_set = NULL;
free(self);
}
-static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
+static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
ia32_prepare_graph,
ia32_before_sched, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
- ia32_lower_spill,
- ia32_lower_reload,
+ ia32_after_ra, /* after register allocation hook */
ia32_codegen /* emit && done */
};
/**
* Initializes the code generator.
*/
-static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
- ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
+static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
+ ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
cg->impl = &ia32_code_gen_if;
- cg->irg = irg;
+ cg->irg = birg->irg;
cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
cg->mod = firm_dbg_register("firm.be.ia32.cg");
cg->out = F;
- cg->arch_env = arch_env;
+ cg->arch_env = birg->main_env->arch_env;
cg->types = pmap_create();
cg->tv_ent = pmap_create();
- cg->noreg_gp = NULL;
- cg->noreg_fp = NULL;
+ cg->birg = birg;
+
+ /* set optimizations */
+ cg->opt.incdec = 0;
+ cg->opt.doam = 1;
+ cg->opt.placecnst = 1;
+ cg->opt.immops = 1;
isa->num_codegens++;
&ia32_gp_regs[REG_ESP],
&ia32_gp_regs[REG_EBP],
-1,
- 0,
- NULL
+ 0
};
/**
isa = xcalloc(1, sizeof(*isa));
memcpy(isa, &ia32_isa_template, sizeof(*isa));
- isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
-
ia32_register_init(isa);
ia32_create_opcodes();
return &ia32_reg_classes[CLASS_ia32_gp];
}
+/**
+ * Produces the type which sits between the stack args and the locals on the stack.
+ * it will contain the return address and space to store the old base pointer.
+ * @return The Firm type modelling the ABI between type.
+ */
+static ir_type *get_between_type(void)
+{
+ static ir_type *between_type = NULL;
+ static entity *old_bp_ent = NULL;
+
+ if(!between_type) {
+ entity *ret_addr_ent;
+ ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
+ ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
+
+ between_type = new_type_class(new_id_from_str("ia32_between_type"));
+ old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
+ ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
+
+ set_entity_offset_bytes(old_bp_ent, 0);
+ set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
+ }
+
+ return between_type;
+}
+
/**
* Get the ABI restrictions for procedure calls.
* @param self The this pointer.
* @param abi The abi object to be modified
*/
void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
+ ir_type *between_type;
ir_type *tp;
ir_mode *mode;
unsigned cc = get_method_calling_convention(method_type);
int i, ignore;
ir_mode **modes;
const arch_register_t *reg;
+ be_abi_call_flags_t call_flags = { 0, 0, 1, 0, 1 };
+
+ /* get the between type and the frame pointer save entity */
+ between_type = get_between_type();
/* set stack parameter passing style */
- be_abi_call_set_flags(abi, BE_ABI_LEFT_TO_RIGHT);
+ be_abi_call_set_flags(abi, call_flags, between_type);
/* collect the mode for each type */
modes = alloca(n * sizeof(modes[0]));
}
else if (n == 1) {
tp = get_method_res_type(method_type, 0);
+ assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- if (mode_is_float(mode)) {
- be_abi_call_res_reg(abi, 1, &ia32_fp_regs[REG_XMM0]);
- }
- else {
- be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EAX]);
- }
+ be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
}
}
return &ia32_irn_handler;
}
-long ia32_handle_call_proj(const void *self, ir_node *proj, int is_keep) {
- ia32_isa_t *isa = (ia32_isa_t *)self;
- long pn = get_Proj_proj(proj);
-
- if (!is_keep) {
- /* It's not a Keep proj, which means, that it is a result proj. */
- /* Possible result proj numbers are 0 and 1 */
- /* Set the correct register (depends on the mode) and the */
- /* corresponding proj number */
- if (mode_is_float(get_irn_mode(proj))) {
- assert(pn == 0 && "only one floating point result supported");
-
- /* Get the proj number for the floating point result */
- pn = ia32_get_reg_projnum(&ia32_fp_regs[REG_XMM0], isa->reg_projnum_map);
- }
- else {
- /* In case of 64bit return value, the result is */
- /* in EDX:EAX and we have two result projs. */
- switch (pn) {
- case 0:
- pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EAX], isa->reg_projnum_map);
- break;
- case 1:
- pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EDX], isa->reg_projnum_map);
- break;
- default:
- assert(0 && "only two int results supported");
- }
- }
-
- /* Set the correct proj number */
- set_Proj_proj(proj, pn);
- }
- else {
- /* Set mode to floating point if required */
- if (!strcmp(ia32_reg_classes[CLASS_ia32_fp].name,
- ia32_projnum_reg_req_map[pn]->req.cls->name)) {
- set_irn_mode(proj, mode_F);
- }
- }
-
- return pn;
-}
-
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
return is_ia32_irn(irn);
}
ia32_get_call_abi,
ia32_get_irn_handler,
ia32_get_code_generator_if,
- ia32_get_list_sched_selector,
- ia32_handle_call_proj
+ ia32_get_list_sched_selector
};
projects / libfirm / blobdiff