Test case for historical reasons

[libfirm] / ir / be / ia32 / bearch_ia32.c

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index f668abc..7267b0c 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -319,9 +319,15 @@ static arch_irn_class_t ia32_classify(const ir_node *irn) {
        if (is_ia32_St(irn))
                classification |= arch_irn_class_store;
 
-       if (is_ia32_need_stackent(irn))
+       if (is_ia32_is_reload(irn))
                classification |= arch_irn_class_reload;
 
+       if (is_ia32_is_spill(irn))
+               classification |= arch_irn_class_spill;
+
+       if (is_ia32_is_remat(irn))
+               classification |= arch_irn_class_remat;
+
        return classification;
 }
 
@@ -497,7 +503,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
                        ir_node *leave;
 
                        /* leave */
-                       leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
+                       leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
                        set_ia32_flags(leave, arch_irn_flags_ignore);
                        curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
                        curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
@@ -920,7 +926,7 @@ static ir_entity *mcount = NULL;
 static void ia32_before_abi(void *self) {
        lower_mode_b_config_t lower_mode_b_config = {
                mode_Iu,  /* lowered mode */
-               mode_Bu,  /* prefered mode for set */
+               mode_Bu,  /* preferred mode for set */
                0,        /* don't lower direct compares */
        };
        ia32_code_gen_t *cg = self;
@@ -971,13 +977,9 @@ static void ia32_prepare_graph(void *self) {
 
 #ifdef FIRM_GRGEN_BE
                case TRANSFORMER_PBQP:
-                       // disable CSE, because of two-step node-construction
-                       set_opt_cse(0);
-
+               case TRANSFORMER_RAND:
                        /* transform nodes into assembler instructions by PBQP magic */
                        ia32_transform_graph_by_pbqp(cg);
-
-                       set_opt_cse(1);
                        break;
 #endif
 
@@ -1028,6 +1030,8 @@ static void turn_back_am(ir_node *node)
        load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
 
        ia32_copy_am_attrs(load, node);
+       if (is_ia32_is_reload(node))
+               set_ia32_is_reload(load);
        set_irn_n(node, n_ia32_mem, new_NoMem());
 
        switch (get_ia32_am_arity(node)) {
@@ -1116,8 +1120,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 
 /**
  * Called before the register allocator.
- * Calculate a block schedule here. We need it for the x87
- * simulator and the emitter.
  */
 static void ia32_before_ra(void *self) {
        ia32_code_gen_t *cg = self;
@@ -1171,6 +1173,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
        set_ia32_ls_mode(new_op, spillmode);
        set_ia32_frame_ent(new_op, ent);
        set_ia32_use_frame(new_op);
+       set_ia32_is_reload(new_op);
 
        DBG_OPT_RELOAD2LD(node, new_op);
 
@@ -1241,6 +1244,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
        set_ia32_ls_mode(store, mode);
        set_ia32_frame_ent(store, ent);
        set_ia32_use_frame(store);
+       set_ia32_is_spill(store);
        SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
        DBG_OPT_SPILL2ST(node, store);
 
@@ -1660,7 +1664,7 @@ static ia32_isa_t ia32_isa_template = {
                &ia32_gp_regs[REG_ESP],  /* stack pointer register */
                &ia32_gp_regs[REG_EBP],  /* base pointer register */
                -1,                      /* stack direction */
-               4,                       /* power of two stack alignment, 2^4 == 16 */
+               2,                       /* power of two stack alignment, 2^2 == 4 */
                NULL,                    /* main environment */
                7,                       /* costs for a spill instruction */
                5,                       /* costs for a reload instruction */
@@ -2119,6 +2123,13 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
        return NULL;
 }
 
+static void ia32_mark_remat(const void *self, ir_node *node) {
+       (void) self;
+       if (is_ia32_irn(node)) {
+               set_ia32_is_remat(node);
+       }
+}
+
 /**
  * Allows or disallows the creation of Psi nodes for the given Phi nodes.
  * @return 1 if allowed, 0 otherwise
@@ -2327,6 +2338,7 @@ static const lc_opt_enum_int_items_t transformer_items[] = {
        { "default", TRANSFORMER_DEFAULT },
 #ifdef FIRM_GRGEN_BE
        { "pbqp",    TRANSFORMER_PBQP    },
+       { "random",  TRANSFORMER_RAND    },
 #endif
        { NULL,      0                   }
 };
@@ -2358,6 +2370,7 @@ const arch_isa_if_t ia32_isa_if = {
        ia32_get_allowed_execution_units,
        ia32_get_machine,
        ia32_get_irg_list,
+       ia32_mark_remat,
        ia32_parse_asm_constraint,
        ia32_is_valid_clobber
 };