#include <math.h>
#include "pseudo_irg.h"
+#include "irarch.h"
#include "irgwalk.h"
#include "irprog.h"
#include "irprintf.h"
#include "debug.h"
#include "error.h"
#include "xmalloc.h"
+#include "irtools.h"
#include "../beabi.h"
#include "../beirg_t.h"
#include "../bemodule.h"
#include "../begnuas.h"
#include "../bestate.h"
+#include "../beflags.h"
#include "bearch_ia32_t.h"
/* TODO: ugly */
static set *cur_reg_set = NULL;
-ir_mode *mode_fpcw = NULL;
+ir_mode *mode_fpcw = NULL;
+ia32_code_gen_t *ia32_current_cg = NULL;
+
+/**
+ * The environment for the intrinsic mapping.
+ */
+static ia32_intrinsic_env_t intrinsic_env = {
+ NULL, /* the isa */
+ NULL, /* the irg, these entities belong to */
+ NULL, /* entity for first div operand (move into FPU) */
+ NULL, /* entity for second div operand (move into FPU) */
+ NULL, /* entity for converts ll -> d */
+ NULL, /* entity for converts d -> ll */
+ NULL, /* entity for __divdi3 library call */
+ NULL, /* entity for __moddi3 library call */
+ NULL, /* entity for __udivdi3 library call */
+ NULL, /* entity for __umoddi3 library call */
+ NULL, /* bias value for conversion from float to unsigned 64 */
+};
+
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
*/
static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
const ir_node *node,
- int pos) {
+ int pos)
+{
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
(void) self;
return arch_no_register_req;
}
-static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void ia32_set_irn_reg(const void *self, ir_node *irn,
+ const arch_register_t *reg)
+{
int pos = 0;
(void) self;
}
}
-static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *ia32_get_irn_reg(const void *self,
+ const ir_node *irn)
+{
int pos = 0;
const arch_register_t *reg = NULL;
(void) self;
if (! is_ia32_irn(irn))
return classification & ~arch_irn_class_normal;
- if (is_ia32_Cnst(irn))
- classification |= arch_irn_class_const;
-
if (is_ia32_Ld(irn))
classification |= arch_irn_class_load;
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
- ia32_am_flavour_t am_flav;
-
if (is_ia32_Pop(irn)) {
int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
if (omit_fp) {
}
}
- am_flav = get_ia32_am_flavour(irn);
- am_flav |= ia32_O;
- set_ia32_am_flavour(irn, am_flav);
-
add_ia32_am_offs_int(irn, bias);
}
}
be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
set_ia32_flags(pop, arch_irn_flags_ignore);
curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
cost += 150;
}
else if (is_ia32_CopyB_i(irn)) {
- int size = get_tarval_long(get_ia32_Immop_tarval(irn));
+ int size = get_ia32_pncode(irn);
cost = 20 + (int)ceil((4/3) * size);
if (ARCH_INTEL(ops->cg->arch))
cost += 150;
return NULL;
/* operand must always be a real operand (not base, index or mem) */
- if (i != 2 && i != 3)
+ if (i != n_ia32_binary_left && i != n_ia32_binary_right)
return NULL;
/* we don't invert address mode operations */
if (get_ia32_op_type(irn) != ia32_Normal)
return NULL;
+ /* TODO: adjust for new immediates... */
+ ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
+ irn);
+ return NULL;
+
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_irn_mode(irn);
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
+#if 0
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
+#endif
break;
case iro_ia32_Sub:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
- if (i == 2) {
- inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
+ if (i == n_ia32_binary_left) {
+ inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
- inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Xor:
+#if 0
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
+#endif
break;
case iro_ia32_Not: {
- inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
- inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
const ir_mode *spillmode = get_spill_mode(op);
(void) self;
- if (! is_ia32_irn(irn) || /* must be an ia32 irn */
- get_irn_arity(irn) != 5 || /* must be a binary operation */
- get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
- ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
- ! ia32_is_spillmode_compatible(mode, spillmode) ||
- (i != 2 && i != 3) || /* a "real" operand position must be requested */
- (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
- is_ia32_use_frame(irn)) /* must not already use frame */
+ if (! is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_ia32_am_arity(irn) != 2 || /* must be a binary operation TODO is this necessary? */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
+ ! ia32_is_spillmode_compatible(mode, spillmode) ||
+ (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
+ is_ia32_use_frame(irn)) /* must not already use frame */
return 0;
+ if (i == n_ia32_binary_left) {
+ const arch_register_req_t *req;
+ if(!is_ia32_commutative(irn))
+ return 0;
+ /* we can't swap left/right for limited registers
+ * (As this (currently) breaks constraint handling copies)
+ */
+ req = get_ia32_in_req(irn, n_ia32_binary_left);
+ if(req->type & arch_register_req_type_limited) {
+ return 0;
+ }
+ }
+
return 1;
}
-static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
+static void ia32_perform_memory_operand(const void *self, ir_node *irn,
+ ir_node *spill, unsigned int i)
+{
const ia32_irn_ops_t *ops = self;
ia32_code_gen_t *cg = ops->cg;
assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
- if (i == 2) {
- ir_node *tmp = get_irn_n(irn, 3);
- set_irn_n(irn, 3, get_irn_n(irn, 2));
- set_irn_n(irn, 2, tmp);
+ if (i == n_ia32_binary_left) {
+ ia32_swap_left_right(irn);
}
set_ia32_op_type(irn, ia32_AddrModeS);
- set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
set_ia32_use_frame(irn);
set_ia32_need_stackent(irn);
- set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
- set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
- set_irn_n(irn, 4, spill);
+ set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
+ set_irn_n(irn, n_ia32_mem, spill);
- //FIXME DBG_OPT_AM_S(reload, irn);
+ /* immediates are only allowed on the right side */
+ if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
+ ia32_swap_left_right(irn);
+ }
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
* |___/
**************************************************/
+static void ia32_before_abi(void *self) {
+ ia32_code_gen_t *cg = self;
+
+ ir_lower_mode_b(cg->irg, mode_Iu, 0);
+ if(cg->dump)
+ be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+}
+
/**
* Transforms the standard firm graph into
* an ia32 firm graph
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
+ /* do local optimisations */
+ optimize_graph_df(cg->irg);
+
+ /* TODO: we often have dead code reachable through out-edges here. So for
+ * now we rebuild edges (as we need correct user count for code selection)
+ */
+#if 1
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
+#endif
+
+ if(cg->dump)
+ be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
+
/* transform nodes into assembler instructions */
ia32_transform_graph(cg);
/* do local optimisations (mainly CSE) */
- local_optimize_graph(cg->irg);
+ optimize_graph_df(cg->irg);
if (cg->dump)
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
if (cg->dump)
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
- /* do code placement, to optimize the position of constants */
+ /* do code placement, (optimize position of constants and argument loads) */
place_code(cg->irg);
if (cg->dump)
(void) self;
}
+static void turn_back_am(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *base = get_irn_n(node, n_ia32_base);
+ ir_node *index = get_irn_n(node, n_ia32_index);
+ ir_node *mem = get_irn_n(node, n_ia32_mem);
+ ir_node *load;
+ ir_node *load_res;
+ ir_node *mem_proj;
+ const ir_edge_t *edge;
+
+ ir_fprintf(stderr, "truning back AM in %+F\n", node);
+
+ load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+ load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+
+ ia32_copy_am_attrs(load, node);
+ set_irn_n(node, n_ia32_mem, new_NoMem());
+
+ if(get_ia32_am_arity(node) == ia32_am_unary) {
+ set_irn_n(node, n_ia32_unary_op, load_res);
+ } else if(get_ia32_am_arity(node) == ia32_am_binary) {
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ } else if(get_ia32_am_arity(node) == ia32_am_ternary) {
+ set_irn_n(node, n_ia32_binary_right, load_res);
+ }
+
+ /* rewire mem-proj */
+ if(get_irn_mode(node) == mode_T) {
+ mem_proj = NULL;
+ foreach_out_edge(node, edge) {
+ ir_node *out = get_edge_src_irn(edge);
+ if(get_Proj_proj(out) == pn_ia32_mem) {
+ mem_proj = out;
+ break;
+ }
+ }
+
+ if(mem_proj != NULL) {
+ set_Proj_pred(mem_proj, load);
+ set_Proj_proj(mem_proj, pn_ia32_Load_M);
+ }
+ }
+
+ set_ia32_op_type(node, ia32_Normal);
+ if(sched_is_scheduled(node))
+ sched_add_before(node, load);
+}
+
+static ir_node *flags_remat(ir_node *node, ir_node *after)
+{
+ /* we should turn back source address mode when rematerializing nodes */
+ ia32_op_type_t type = get_ia32_op_type(node);
+ ir_node *copy;
+
+ if (type == ia32_AddrModeS) {
+ turn_back_am(node);
+ } else if (type == ia32_AddrModeD) {
+ /* TODO implement this later... */
+ panic("found DestAM with flag user %+F this should not happen", node);
+ } else {
+ assert(type == ia32_Normal);
+ }
+
+ copy = exact_copy(node);
+ sched_add_after(after, copy);
+
+ return copy;
+}
+
/**
* Called before the register allocator.
* Calculate a block schedule here. We need it for the x87
* simulator and the emitter.
*/
static void ia32_before_ra(void *self) {
- ia32_code_gen_t *cg = self;
+ ia32_code_gen_t *cg = self;
/* setup fpu rounding modes */
ia32_setup_fpu_mode(cg);
+
+ /* fixup flags */
+ be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
+ &flags_remat);
+
+ ia32_add_missing_keeps(cg);
}
if (mode_is_float(spillmode)) {
if (USE_SSE2(cg))
- new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
+ new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
}
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
if (sched_point) {
sched_add_after(sched_point, new_op);
-#ifdef SCHEDULE_PROJS
- sched_add_after(new_op, proj);
-#endif
sched_remove(node);
}
if (mode_is_float(mode)) {
if (USE_SSE2(cg))
- store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
else
- store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem, mode);
+ store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
} else if (get_mode_size_bits(mode) == 128) {
// Spill 128 bit SSE registers
- store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
} else if (get_mode_size_bits(mode) == 8) {
- store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
} else {
- store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
+ store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
}
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
+ ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
- set_ia32_am_flavour(push, ia32_B);
set_ia32_ls_mode(push, mode_Is);
sched_add_before(schedpoint, push);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *frame = get_irg_frame(irg);
- ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
+ ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
- set_ia32_am_flavour(pop, ia32_am_OB);
set_ia32_ls_mode(pop, mode_Is);
sched_add_before(schedpoint, pop);
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) {
if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = get_mode_size_bytes(mode);
+ const ir_mode *mode = get_ia32_ls_mode(node);
+ const ia32_attr_t *attr = get_ia32_attr_const(node);
+ int align = get_mode_size_bytes(mode);
+
+ if(attr->data.need_64bit_stackent) {
+ mode = mode_Ls;
+ }
+ if(attr->data.need_32bit_stackent) {
+ mode = mode_Is;
+ }
be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
|| is_ia32_vfld(node)) {
const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_SetST0(node)) {
- const ir_mode *mode = get_ia32_ls_mode(node);
- int align = 4;
- be_node_needs_frame_entity(env, node, mode, align);
} else {
#ifndef NDEBUG
assert(is_ia32_St(node) ||
is_ia32_xStoreSimple(node) ||
is_ia32_vfst(node) ||
is_ia32_vfist(node) ||
- is_ia32_GetST0(node) ||
is_ia32_FnstCW(node));
#endif
}
be_free_frame_entity_coalescer(fec_env);
irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
-
- ia32_finish_irg(irg, cg);
}
/**
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- /* if we do x87 code generation, rewrite all the virtual instructions and registers */
- if (cg->used_fp == fp_x87 || cg->force_sim) {
+ ia32_finish_irg(irg, cg);
+
+ /* we might have to rewrite x87 virtual registers */
+ if (cg->do_x87_sim) {
x87_simulate_graph(cg->arch_env, cg->birg);
}
/* remove it from the isa */
cg->isa->cg = NULL;
+ assert(ia32_current_cg == cg);
+ ia32_current_cg = NULL;
+
/* de-allocate code generator */
del_set(cg->reg_set);
free(cg);
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
- NULL, /* before abi introduce hook */
+ ia32_before_abi, /* before abi introduce hook */
ia32_prepare_graph,
NULL, /* spill */
ia32_before_sched, /* before scheduling hook */
cg->birg = birg;
cg->blk_sched = NULL;
cg->fp_kind = isa->fp_kind;
- cg->used_fp = fp_none;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
/* copy optimizations from isa for easier access */
ia32_irn_ops.cg = cg;
+ assert(ia32_current_cg == NULL);
+ ia32_current_cg = cg;
+
return (arch_code_generator_t *)cg;
}
* Set output modes for GCC
*/
static const tarval_mode_info mo_integer = {
- TVO_DECIMAL,
- NULL,
+ TVO_HEX,
+ "0x",
NULL,
};
#endif
};
+static void set_arch_costs(enum cpu_support arch);
+
/**
* Initializes the backend ISA.
*/
ia32_register_init();
ia32_create_opcodes();
+ set_arch_costs(isa->opt_arch);
+
if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
(ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
/* no SSE2 for these cpu's */
obstack_init(isa->name_obst);
#endif /* NDEBUG */
+ /* enter the ISA object into the intrinsic environment */
+ intrinsic_env.isa = isa;
ia32_handle_intrinsics();
/* needed for the debug support */
*/
static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
{
- ir_node *cmp, *cmp_a, *phi;
- ir_mode *mode;
-
-/* we don't want long long an floating point Psi */
-#define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
-
- if (get_irn_mode(sel) != mode_b)
- return 0;
-
- cmp = get_Proj_pred(sel);
- cmp_a = get_Cmp_left(cmp);
- mode = get_irn_mode(cmp_a);
-
- if (IS_BAD_PSI_MODE(mode))
- return 0;
+ ir_node *phi;
+
+ (void)sel;
+ (void)i;
+ (void)j;
+
+#if 1
+ if(is_Proj(sel)) {
+ ir_node *pred = get_Proj_pred(sel);
+ if(is_Cmp(pred)) {
+ ir_node *left = get_Cmp_left(pred);
+ ir_mode *cmp_mode = get_irn_mode(left);
+ if(mode_is_float(cmp_mode))
+ return 0;
+ }
+ }
+#endif
/* check the Phi nodes */
for (phi = phi_list; phi; phi = get_irn_link(phi)) {
- ir_node *pred_i = get_irn_n(phi, i);
- ir_node *pred_j = get_irn_n(phi, j);
- ir_mode *mode_i = get_irn_mode(pred_i);
- ir_mode *mode_j = get_irn_mode(pred_j);
+ ir_mode *mode = get_irn_mode(phi);
- if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
+ if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
return 0;
}
-#undef IS_BAD_PSI_MODE
-
return 1;
}
-static ia32_intrinsic_env_t intrinsic_env = {
- NULL, /**< the irg, these entities belong to */
- NULL, /**< entity for first div operand (move into FPU) */
- NULL, /**< entity for second div operand (move into FPU) */
- NULL, /**< entity for converts ll -> d */
- NULL, /**< entity for converts d -> ll */
+typedef struct insn_const {
+ int add_cost; /**< cost of an add instruction */
+ int lea_cost; /**< cost of a lea instruction */
+ int const_shf_cost; /**< cost of a constant shift instruction */
+ int cost_mul_start; /**< starting cost of a multiply instruction */
+ int cost_mul_bit; /**< cost of multiply for every set bit */
+} insn_const;
+
+/* costs for the i386 */
+static const insn_const i386_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 6, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
+};
+
+/* costs for the i486 */
+static const insn_const i486_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 2, /* cost of a constant shift instruction */
+ 12, /* starting cost of a multiply instruction */
+ 1 /* cost of multiply for every set bit */
};
+/* costs for the Pentium */
+static const insn_const pentium_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 11, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium Pro */
+static const insn_const pentiumpro_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the K6 */
+static const insn_const k6_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 3, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Athlon */
+static const insn_const athlon_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 5, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Pentium 4 */
+static const insn_const pentium4_cost = {
+ 1, /* cost of an add instruction */
+ 3, /* cost of a lea instruction */
+ 4, /* cost of a constant shift instruction */
+ 15, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the Core */
+static const insn_const core_cost = {
+ 1, /* cost of an add instruction */
+ 1, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 10, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+/* costs for the generic */
+static const insn_const generic_cost = {
+ 1, /* cost of an add instruction */
+ 2, /* cost of a lea instruction */
+ 1, /* cost of a constant shift instruction */
+ 4, /* starting cost of a multiply instruction */
+ 0 /* cost of multiply for every set bit */
+};
+
+static const insn_const *arch_costs = &generic_cost;
+
+static void set_arch_costs(enum cpu_support arch) {
+ switch (arch) {
+ case arch_i386:
+ arch_costs = &i386_cost;
+ break;
+ case arch_i486:
+ arch_costs = &i486_cost;
+ break;
+ case arch_pentium:
+ case arch_pentium_mmx:
+ arch_costs = &pentium_cost;
+ break;
+ case arch_pentium_pro:
+ case arch_pentium_2:
+ case arch_pentium_3:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_pentium_4:
+ arch_costs = &pentium4_cost;
+ break;
+ case arch_pentium_m:
+ arch_costs = &pentiumpro_cost;
+ break;
+ case arch_core:
+ arch_costs = &core_cost;
+ break;
+ case arch_k6:
+ arch_costs = &k6_cost;
+ break;
+ case arch_athlon:
+ case arch_athlon_64:
+ case arch_opteron:
+ arch_costs = &athlon_cost;
+ break;
+ case arch_generic:
+ default:
+ arch_costs = &generic_cost;
+ }
+}
+
+/**
+ * Evaluate a given simple instruction.
+ */
+static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
+ int cost;
+
+ switch (kind) {
+ case MUL:
+ cost = arch_costs->cost_mul_start;
+ if (arch_costs->cost_mul_bit > 0) {
+ char *bitstr = get_tarval_bitpattern(tv);
+ int i;
+
+ for (i = 0; bitstr[i] != '\0'; ++i) {
+ if (bitstr[i] == '1') {
+ cost += arch_costs->cost_mul_bit;
+ }
+ }
+ free(bitstr);
+ }
+ return cost;
+ case LEA:
+ return arch_costs->lea_cost;
+ case ADD:
+ case SUB:
+ return arch_costs->add_cost;
+ case SHIFT:
+ return arch_costs->const_shf_cost;
+ case ZERO:
+ return arch_costs->add_cost;
+ default:
+ return 1;
+ }
+}
+
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *ia32_get_libfirm_params(void) {
- static const opt_if_conv_info_t ifconv = {
+ static const ir_settings_if_conv_t ifconv = {
4, /* maxdepth, doesn't matter for Psi-conversion */
ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
};
- static const arch_dep_params_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
- 31, /* maximum shift amount */
+ static const ir_settings_arch_dep_t ad = {
+ 1, /* also use subs */
+ 4, /* maximum shifts */
+ 31, /* maximum shift amount */
+ ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* allow Mulus */
NULL, /* will be set later */
ia32_create_intrinsic_fkt,
&intrinsic_env, /* context for ia32_create_intrinsic_fkt */
- NULL, /* will be set later */
+ NULL, /* will be set below */
};
p.dep_param = &ad;
{ "athlon", arch_athlon, },
{ "athlon64", arch_athlon_64, },
{ "opteron", arch_opteron, },
+ { "generic", arch_generic, },
{ NULL, 0 }
};
projects / libfirm / blobdiff