#include "../be.h"
#include "../be_t.h"
#include "../beirgmod.h"
+#include "../be_dbgout.h"
+#include "../beblocksched.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
/* TODO: ugly */
static set *cur_reg_set = NULL;
-#undef is_Start
-#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
-
/* Creates the unique per irg GP NoReg node. */
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
}
+/**
+ * Returns gp_noreg or fp_noreg, depending in input requirements.
+ */
+ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
+ arch_register_req_t req;
+ const arch_register_req_t *p_req;
+
+ p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
+ assert(p_req && "Missing register requirements");
+ if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
+ return ia32_new_NoReg_gp(cg);
+ else
+ return ia32_new_NoReg_fp(cg);
+}
+
/**************************************************
* _ _ _ __
* | | | (_)/ _|
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
-
/**
* Return register requirements for an ia32 node.
* If the node returns a tuple (mode_T) then the proj's
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
if (is_Proj(irn)) {
- if (pos == -1) {
- node_pos = ia32_translate_proj_pos(irn);
- }
- else {
- node_pos = pos;
+ if(pos >= 0) {
+ DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
+ return NULL;
}
- irn = my_skip_proj(irn);
+ node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
+ irn = skip_Proj(irn);
DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
}
if (is_ia32_irn(irn)) {
- if (pos >= 0) {
- irn_req = get_ia32_in_req(irn, pos);
- }
- else {
- irn_req = get_ia32_out_req(irn, node_pos);
- }
+ irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
if (is_Proj(irn)) {
- pos = ia32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ pos = get_Proj_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_ia32_irn(irn)) {
return NULL;
}
- pos = ia32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ pos = get_Proj_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_ia32_irn(irn)) {
- const arch_register_t **slots;
- slots = get_ia32_slots(irn);
- reg = slots[pos];
+ /* retrieve "real" x87 register */
+ if (ia32_has_x87_register(irn))
+ reg = get_ia32_attr(irn)->x87[pos + 2];
+ else {
+ const arch_register_t **slots;
+ slots = get_ia32_slots(irn);
+ reg = slots[pos];
+ }
}
else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
arch_irn_class_t classification = arch_irn_class_normal;
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
if (is_cfop(irn))
classification |= arch_irn_class_branch;
}
static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
+ arch_irn_flags_t flags = arch_irn_flags_none;
- if(is_Proj(irn)) {
- ir_node *pred = get_Proj_pred(irn);
- if(is_ia32_Push(pred) && get_Proj_proj(irn) == pn_ia32_Push_stack) {
- return arch_irn_flags_modify_sp;
- }
- if(is_ia32_Pop(pred) && get_Proj_proj(irn) == pn_ia32_Pop_stack) {
- return arch_irn_flags_modify_sp;
- }
- if(is_ia32_AddSP(pred) && get_Proj_proj(irn) == pn_ia32_AddSP_stack) {
- return arch_irn_flags_modify_sp;
- }
+ if (is_Proj(irn) && is_ia32_irn(get_Proj_pred(irn))) {
+ flags |= get_ia32_out_flags(irn, get_Proj_proj(irn));
}
- irn = my_skip_proj(irn);
+ irn = skip_Proj(irn);
if (is_ia32_irn(irn))
- return get_ia32_flags(irn);
- else {
- if (is_Unknown(irn))
- return arch_irn_flags_ignore;
- return 0;
- }
+ flags |= get_ia32_flags(irn);
+ else if (is_Unknown(irn))
+ flags = arch_irn_flags_ignore;
+
+ return flags;
}
+/**
+ * The IA32 ABI callback object.
+ */
+typedef struct {
+ be_abi_call_flags_bits_t flags; /**< The call flags. */
+ const arch_isa_t *isa; /**< The ISA handle. */
+ const arch_env_t *aenv; /**< The architecture environment. */
+ ir_graph *irg; /**< The associated graph. */
+} ia32_abi_env_t;
+
static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
if (get_ia32_frame_ent(irn)) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
- /* Pop nodes modify the stack pointer before calculating the destination
- * address, so fix this here
- */
if(is_ia32_Pop(irn)) {
- bias -= 4;
+ int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
+ if (omit_fp) {
+ /* Pop nodes modify the stack pointer before calculating the destination
+ * address, so fix this here
+ */
+ bias -= 4;
+ }
}
DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
if(is_Proj(irn)) {
- int proj = get_Proj_proj(irn);
+ long proj = get_Proj_proj(irn);
ir_node *pred = get_Proj_pred(irn);
- if(is_ia32_Push(pred) && proj == 0)
+ if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
return 4;
- if(is_ia32_Pop(pred) && proj == 1)
+ if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
return -4;
}
return 0;
}
-typedef struct {
- be_abi_call_flags_bits_t flags;
- const arch_isa_t *isa;
- const arch_env_t *aenv;
- ir_graph *irg;
-} ia32_abi_env_t;
-
-static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
-{
- ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- env->aenv = aenv;
- env->isa = aenv->isa;
- return env;
-}
-
/**
* Put all registers which are saved by the prologue/epilogue in a set.
*
ir_node *bl = get_irg_start_block(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *push;
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
*mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
}
else {
+ ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *pop;
/* copy ebp to esp */
curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
set_ia32_flags(pop, arch_irn_flags_ignore);
curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
}
+/**
+ * Initialize the callback object.
+ * @param call The call object.
+ * @param aenv The architecture environment.
+ * @param irg The graph with the method.
+ * @return Some pointer. This pointer is passed to all other callback functions as self object.
+ */
+static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
+{
+ ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ env->flags = fl.bits;
+ env->irg = irg;
+ env->aenv = aenv;
+ env->isa = aenv->isa;
+ return env;
+}
+
+/**
+ * Destroy the callback object.
+ * @param self The callback object.
+ */
+static void ia32_abi_done(void *self) {
+ free(self);
+}
+
/**
* Produces the type which sits between the stack args and the locals on the stack.
* it will contain the return address and space to store the old base pointer.
}
static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
+ const ia32_irn_ops_t *ops = self;
+ ia32_code_gen_t *cg = ops->cg;
+
assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
if (i == 2) {
set_ia32_op_type(irn, ia32_AddrModeS);
set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
- //TODO this will fail, if spill is a PhiM (give PhiMs entities?)
- set_ia32_frame_ent(irn, be_get_frame_entity(spill));
set_ia32_use_frame(irn);
set_ia32_got_reload(irn);
We would need cg object to get a real noreg, but we cannot
access it from here.
*/
- set_irn_n(irn, 3, get_irn_n(irn, 1));
+ set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
//FIXME DBG_OPT_AM_S(reload, irn);
}
static const be_abi_callbacks_t ia32_abi_callbacks = {
ia32_abi_init,
- free,
+ ia32_abi_done,
ia32_abi_get_between_type,
ia32_abi_dont_save_regs,
ia32_abi_prologue,
}
static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
- int i;
+ int i, arity;
ir_mode *mode;
- ir_node *mem_proj;
+ ir_node *mem_proj = NULL;
if (is_Block(irn))
return;
mode = get_irn_mode(irn);
/* check if we already saw this node or the node has more than one user */
- if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
+ if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
return;
+ };
/* mark irn visited */
bitset_add_irn(already_visited, irn);
/* non-Tuple nodes with one user: ok, return */
- if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
+ if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
return;
+ }
/* tuple node has one user which is not the mem proj-> ok */
if (mode == mode_T && get_irn_n_edges(irn) == 1) {
mem_proj = ia32_get_proj_for_mode(irn, mode_M);
- if (! mem_proj)
+ if (mem_proj == NULL) {
return;
+ }
}
- for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
+ arity = get_irn_arity(irn);
+ for (i = 0; i < arity; ++i) {
ir_node *pred = get_irn_n(irn, i);
/* do not follow memory edges or we will accidentally remove stores */
- if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
+ if (get_irn_mode(pred) == mode_M) {
+ if(mem_proj != NULL) {
+ edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
+ mem_proj = NULL;
+ }
continue;
+ }
set_irn_n(irn, i, new_Bad());
remove_unused_nodes(pred, already_visited);
}
+ // we need to set the presd to Bad again to also get the memory edges
+ arity = get_irn_arity(irn);
+ for (i = 0; i < arity; ++i) {
+ set_irn_n(irn, i, new_Bad());
+ }
+
if (sched_is_scheduled(irn)) {
- set_irn_n(irn, 0, new_Bad());
- set_irn_n(irn, 1, new_Bad());
- set_irn_n(irn, 2, new_Bad());
sched_remove(irn);
}
}
*/
static void ia32_before_ra(void *self) {
ia32_code_gen_t *cg = self;
- bitset_t *already_visited = bitset_irg_malloc(cg->irg);
+ bitset_t *already_visited = bitset_irg_alloca(cg->irg);
/*
Handle special case:
We need to remove those Loads and all other nodes which won't be used
after removing the Load from schedule.
*/
- irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
- bitset_free(already_visited);
+ irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
}
else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
- else {
+ else
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
- }
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
DBG_OPT_RELOAD2LD(irn, new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
exchange(irn, proj);
}
-static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent, const char *offset) {
+static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *frame = get_irg_frame(env->irg);
- ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, sp, noreg, mem);
+ ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
set_ia32_am_flavour(push, ia32_B);
set_ia32_ls_mode(push, mode_Is);
- if(offset != NULL)
- add_ia32_am_offs(push, offset);
sched_add_before(schedpoint, push);
return push;
}
-static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent, const char *offset) {
- ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, sp, new_NoMem());
+static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *frame = get_irg_frame(env->irg);
+
+ ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
set_ia32_am_flavour(pop, ia32_B);
set_ia32_ls_mode(pop, mode_Is);
- if(offset != NULL)
- add_ia32_am_offs(pop, offset);
sched_add_before(schedpoint, pop);
return pop;
}
-static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint, const ir_node *oldsp) {
- ir_mode *spmode = get_irn_mode(oldsp);
- const arch_register_t *spreg = arch_get_irn_register(env->cg->arch_env, oldsp);
+static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
+ ir_mode *spmode = mode_Iu;
+ const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
ir_node *sp;
sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
return sp;
}
+/**
+ * Transform memperm, currently we do this the ugly way and produce
+ * push/pop into/from memory cascades. This is possible without using
+ * any registers.
+ */
static void transform_MemPerm(ia32_transform_env_t *env) {
- /*
- * Transform memperm, currently we do this the ugly way and produce
- * push/pop into/from memory cascades. This is possible without using
- * any registers.
- */
ir_node *node = env->irn;
int i, arity;
- ir_node *sp = get_irn_n(node, 0);
+ ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
const ir_edge_t *edge;
const ir_edge_t *next;
ir_node **pops;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- push = create_push(env, node, sp, mem, ent, NULL);
- sp = create_spproj(env, push, 0, node, sp);
+ push = create_push(env, node, sp, mem, ent);
+ sp = create_spproj(env, push, 0, node);
if(entbits == 64) {
// add another push after the first one
- push = create_push(env, node, sp, mem, ent, "4");
- sp = create_spproj(env, push, 0, node, sp);
+ push = create_push(env, node, sp, mem, ent);
+ add_ia32_am_offs_int(push, 4);
+ sp = create_spproj(env, push, 0, node);
}
set_irn_n(node, i, new_Bad());
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- pop = create_pop(env, node, sp, ent, NULL);
+ pop = create_pop(env, node, sp, ent);
if(entbits == 64) {
// add another pop after the first one
- sp = create_spproj(env, pop, 1, node, sp);
- pop = create_pop(env, node, sp, ent, "4");
+ sp = create_spproj(env, pop, 1, node);
+ pop = create_pop(env, node, sp, ent);
+ add_ia32_am_offs_int(pop, 4);
}
- //if(i != 0) {
- sp = create_spproj(env, pop, 1, node, sp);
- //}
+ sp = create_spproj(env, pop, 1, node);
pops[i] = pop;
}
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- // Matze: disabled for now, as the irextbb algo sometimes returns extbb in
- // the wrong order if the graph has critical edges
- be_remove_empty_blocks(irg);
+ //be_remove_empty_blocks(irg);
+ cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
- cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
+ //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
/* if we do x87 code generation, rewrite all the virtual instructions and registers */
if (cg->used_fp == fp_x87 || cg->force_sim) {
};
/*
-* set the tarval output mode to C-semantics
-*/
+ * set the tarval output mode of all integer modes to decimal
+ */
static void set_tarval_output_modes(void)
{
- set_tarval_mode_output_option(get_modeLs(), &mo_integer);
- set_tarval_mode_output_option(get_modeLu(), &mo_integer);
- set_tarval_mode_output_option(get_modeIs(), &mo_integer);
- set_tarval_mode_output_option(get_modeIu(), &mo_integer);
- set_tarval_mode_output_option(get_modeHs(), &mo_integer);
- set_tarval_mode_output_option(get_modeHu(), &mo_integer);
- set_tarval_mode_output_option(get_modeBs(), &mo_integer);
- set_tarval_mode_output_option(get_modeBu(), &mo_integer);
- set_tarval_mode_output_option(get_modeC(), &mo_integer);
- set_tarval_mode_output_option(get_modeU(), &mo_integer);
- set_tarval_mode_output_option(get_modeIu(), &mo_integer);
+ int i;
+
+ for (i = get_irp_n_modes() - 1; i >= 0; --i) {
+ ir_mode *mode = get_irp_mode(i);
+
+ if (mode_is_int(mode))
+ set_tarval_mode_output_option(mode, &mo_integer);
+ }
}
#endif /* NDEBUG */
ia32_handle_intrinsics();
- ia32_switch_section(NULL, NO_SECTION);
+ ia32_switch_section(isa->out, NO_SECTION);
fprintf(isa->out, "\t.intel_syntax\n");
+ /* needed for the debug support */
+ ia32_switch_section(isa->out, SECTION_TEXT);
+ fprintf(isa->out, ".Ltext0:\n");
+
inited = 1;
return isa;
/* set stack parameters */
for (i = stack_idx; i < n; i++) {
- be_abi_call_param_stack(abi, i, 1, 0, 0);
+ /* parameters on the stack are 32 bit aligned */
+ be_abi_call_param_stack(abi, i, 4, 0, 0);
}
tp = get_method_res_type(method_type, 1);
mode = get_type_mode(tp);
- assert(!mode_is_float(mode) && "two FP results not supported");
+ assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- reg = mode_is_float(mode) ?
- (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
- &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
be_abi_call_res_reg(abi, 0, reg);
}
projects / libfirm / blobdiff