#include "ia32_common_transform.h"
#include "ia32_transform.h"
#include "ia32_emitter.h"
-#include "ia32_map_regs.h"
#include "ia32_optimize.h"
#include "ia32_x87.h"
#include "ia32_dbg_stat.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-ir_mode *mode_fpcw = NULL;
+ir_mode *ia32_mode_fpcw = NULL;
/** The current omit-fp state */
static unsigned ia32_curr_fp_ommitted = 0;
static arch_irn_class_t ia32_classify(const ir_node *irn)
{
- arch_irn_class_t classification = 0;
+ arch_irn_class_t classification = arch_irn_class_none;
assert(is_ia32_irn(irn));
*/
static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
ir_graph *irg = env->irg;
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
*/
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
*/
static ir_type *ia32_abi_get_between_type(void *self)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = (ia32_abi_env_t*)self;
ia32_build_between_type();
return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
dump_ir_graph(irg, "place");
}
-ir_node *turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_graph *irg = get_irn_irg(node);
type = get_ia32_op_type(node);
switch (type) {
case ia32_AddrModeS:
- turn_back_am(node);
+ ia32_turn_back_am(node);
break;
case ia32_AddrModeD:
*/
static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
{
- be_fec_env_t *env = data;
+ be_fec_env_t *env = (be_fec_env_t*)data;
const ir_mode *mode;
int align;
/* we might have to rewrite x87 virtual registers */
if (irg_data->do_x87_sim) {
- x87_simulate_graph(irg);
+ ia32_x87_simulate_graph(irg);
}
/* do peephole optimisations */
}
}
-const arch_isa_if_t ia32_isa_if;
+extern const arch_isa_if_t ia32_isa_if;
/**
* The template that generates a new ISA object.
&ia32_isa_if, /* isa interface implementation */
N_IA32_REGISTERS,
ia32_registers,
+ N_IA32_CLASSES,
+ ia32_reg_classes,
&ia32_registers[REG_ESP], /* stack pointer register */
&ia32_registers[REG_EBP], /* base pointer register */
&ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
5, /* costs for a reload instruction */
false, /* no custom abi handling */
},
- NULL, /* 16bit register names */
- NULL, /* 8bit register names */
- NULL, /* 8bit register names high */
NULL, /* types */
NULL, /* tv_ents */
NULL, /* abstract machine */
*/
static arch_env_t *ia32_init(FILE *file_handle)
{
- static int inited = 0;
- ia32_isa_t *isa;
+ ia32_isa_t *isa = XMALLOC(ia32_isa_t);
int i, n;
- if (inited)
- return NULL;
- inited = 1;
-
set_tarval_output_modes();
- isa = XMALLOC(ia32_isa_t);
memcpy(isa, &ia32_isa_template, sizeof(*isa));
- if (mode_fpcw == NULL) {
- mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ if (ia32_mode_fpcw == NULL) {
+ ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
}
ia32_register_init();
ia32_create_opcodes(&ia32_irn_ops);
be_emit_init(file_handle);
- isa->regs_16bit = pmap_create();
- isa->regs_8bit = pmap_create();
- isa->regs_8bit_high = pmap_create();
isa->types = pmap_create();
isa->tv_ent = pmap_create();
isa->cpu = ia32_init_machine_description();
- ia32_build_16bit_reg_map(isa->regs_16bit);
- ia32_build_8bit_reg_map(isa->regs_8bit);
- ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
-
/* enter the ISA object into the intrinsic environment */
intrinsic_env.isa = isa;
*/
static void ia32_done(void *self)
{
- ia32_isa_t *isa = self;
+ ia32_isa_t *isa = (ia32_isa_t*)self;
/* emit now all global declarations */
be_gas_emit_decls(isa->base.main_env);
- pmap_destroy(isa->regs_16bit);
- pmap_destroy(isa->regs_8bit);
- pmap_destroy(isa->regs_8bit_high);
pmap_destroy(isa->tv_ent);
pmap_destroy(isa->types);
}
-/**
- * Return the number of register classes for this architecture.
- * We report always these:
- * - the general purpose registers
- * - the SSE floating point register set
- * - the virtual floating point registers
- * - the SSE vector register set
- */
-static unsigned ia32_get_n_reg_class(void)
-{
- return N_IA32_CLASSES;
-}
-
-/**
- * Return the register class for index i.
- */
-static const arch_register_class_t *ia32_get_reg_class(unsigned i)
-{
- assert(i < N_IA32_CLASSES);
- return &ia32_reg_classes[i];
-}
-
/**
* Get the register class which shall be used to store a value of a given mode.
* @param self The this pointer.
* or max(a, b) = a >= b ? a : b
* (Note we only handle float min/max here)
*/
- pnc = get_Proj_proj(sel);
+ pnc = get_Proj_pn_cmp(sel);
switch (pnc) {
case pn_Cmp_Ge:
case pn_Cmp_Gt:
ir_node *st;
/* mov ecx,<env> */
- st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, env, 0);
+ st = new_r_Store(block, mem, p, env, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
/* jmp <callee> */
- st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), 0);
+ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
- st = new_r_Store(block, mem, p, callee, 0);
+ st = new_r_Store(block, mem, p, callee, cons_none);
mem = new_r_Proj(st, mode_M, pn_Store_M);
p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
static const ir_settings_arch_dep_t ad = {
1, /* also use subs */
4, /* maximum shifts */
- 31, /* maximum shift amount */
+ 63, /* maximum shift amount */
ia32_evaluate_insn, /* evaluate the instruction sequence */
1, /* allow Mulhs */
1, /* support inline assembly */
1, /* support Rotl nodes */
0, /* little endian */
- ia32_lower_for_target,
NULL, /* will be set later */
ia32_is_mux_allowed,
NULL, /* float arithmetic mode, will be set below */
const arch_isa_if_t ia32_isa_if = {
ia32_init,
+ ia32_lower_for_target,
ia32_done,
ia32_handle_intrinsics,
- ia32_get_n_reg_class,
- ia32_get_reg_class,
ia32_get_reg_class_for_mode,
ia32_get_call_abi,
ia32_get_reg_class_alignment,
projects / libfirm / blobdiff