#include <libcore/lc_opts_enum.h>
#endif /* WITH_LIBCORE */
+#include <math.h>
+
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irprog.h"
#include "../belower.h"
#include "../besched_t.h"
#include "../be.h"
+#include "../be_t.h"
+#include "../beirgmod.h"
+#include "../be_dbgout.h"
+#include "../beblocksched.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
#include "ia32_x87.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
+#include "ia32_util.h"
#define DEBUG_MODULE "firm.be.ia32.isa"
/* TODO: ugly */
static set *cur_reg_set = NULL;
-#undef is_Start
-#define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
-
/* Creates the unique per irg GP NoReg node. */
ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
}
-/* returns the first Proj with given mode from mode_T node */
-static ir_node *get_proj_for_mode(ir_node *node, ir_mode *mode) {
- const ir_edge_t *edge;
-
- assert(get_irn_mode(node) == mode_T && "Need mode_T node.");
-
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- if (get_irn_mode(proj) == mode)
- return proj;
- }
-
- return NULL;
+/**
+ * Returns gp_noreg or fp_noreg, depending in input requirements.
+ */
+ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
+ arch_register_req_t req;
+ const arch_register_req_t *p_req;
+
+ p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
+ assert(p_req && "Missing register requirements");
+ if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
+ return ia32_new_NoReg_gp(cg);
+ else
+ return ia32_new_NoReg_fp(cg);
}
/**************************************************
* |___/
**************************************************/
-static ir_node *my_skip_proj(const ir_node *n) {
- while (is_Proj(n))
- n = get_Proj_pred(n);
- return (ir_node *)n;
-}
-
-
/**
* Return register requirements for an ia32 node.
* If the node returns a tuple (mode_T) then the proj's
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
if (is_Proj(irn)) {
- if (pos == -1) {
- node_pos = ia32_translate_proj_pos(irn);
- }
- else {
- node_pos = pos;
+ if(pos >= 0) {
+ DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
+ return NULL;
}
- irn = my_skip_proj(irn);
+ node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
+ irn = skip_Proj(irn);
DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
}
if (is_ia32_irn(irn)) {
- if (pos >= 0) {
- irn_req = get_ia32_in_req(irn, pos);
- }
- else {
- irn_req = get_ia32_out_req(irn, node_pos);
+ irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
+ if (irn_req == NULL) {
+ /* no requirements */
+ return NULL;
}
DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
if (is_Proj(irn)) {
- pos = ia32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ pos = get_Proj_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_ia32_irn(irn)) {
return NULL;
}
- pos = ia32_translate_proj_pos(irn);
- irn = my_skip_proj(irn);
+ pos = get_Proj_proj(irn);
+ irn = skip_Proj(irn);
}
if (is_ia32_irn(irn)) {
}
static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
+ arch_irn_class_t classification = arch_irn_class_normal;
+
+ irn = skip_Proj(irn);
+
if (is_cfop(irn))
- return arch_irn_class_branch;
- else if (is_ia32_Cnst(irn))
- return arch_irn_class_const;
- else if (is_ia32_Ld(irn))
- return arch_irn_class_load;
- else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
- return arch_irn_class_store;
- else if (is_ia32_irn(irn))
- return arch_irn_class_normal;
- else
- return 0;
+ classification |= arch_irn_class_branch;
+
+ if (! is_ia32_irn(irn))
+ return classification & ~arch_irn_class_normal;
+
+ if (is_ia32_Cnst(irn))
+ classification |= arch_irn_class_const;
+
+ if (is_ia32_Ld(irn))
+ classification |= arch_irn_class_load;
+
+ if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+ classification |= arch_irn_class_store;
+
+ if (is_ia32_got_reload(irn))
+ classification |= arch_irn_class_reload;
+
+ return classification;
}
static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
- irn = my_skip_proj(irn);
- if (is_ia32_irn(irn))
- return get_ia32_flags(irn);
+ arch_irn_flags_t flags;
+ ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
+
+ if (is_Unknown(irn))
+ flags = arch_irn_flags_ignore;
else {
- if (is_Unknown(irn))
- return arch_irn_flags_ignore;
- return 0;
+ /* pred is only set, if we have a Proj */
+ flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
+
+ irn = skip_Proj(irn);
+ if (is_ia32_irn(irn))
+ flags |= get_ia32_flags(irn);
}
+
+ return flags;
}
+/**
+ * The IA32 ABI callback object.
+ */
+typedef struct {
+ be_abi_call_flags_bits_t flags; /**< The call flags. */
+ const arch_isa_t *isa; /**< The ISA handle. */
+ const arch_env_t *aenv; /**< The architecture environment. */
+ ir_graph *irg; /**< The associated graph. */
+} ia32_abi_env_t;
+
static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
-static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
+static void ia32_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
+ set_ia32_frame_ent(irn, ent);
+}
+
+static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
char buf[64];
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
+ if(is_ia32_Pop(irn)) {
+ int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
+ if (omit_fp) {
+ /* Pop nodes modify the stack pointer before calculating the destination
+ * address, so fix this here
+ */
+ bias -= 4;
+ }
+ }
+
DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
+
snprintf(buf, sizeof(buf), "%d", bias);
if (get_ia32_op_type(irn) == ia32_Normal) {
set_ia32_cnst(irn, buf);
- }
- else {
+ } else {
add_ia32_am_offs(irn, buf);
am_flav |= ia32_O;
set_ia32_am_flavour(irn, am_flav);
}
}
-typedef struct {
- be_abi_call_flags_bits_t flags;
- const arch_isa_t *isa;
- const arch_env_t *aenv;
- ir_graph *irg;
-} ia32_abi_env_t;
+static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
+ if(is_Proj(irn)) {
+ long proj = get_Proj_proj(irn);
+ ir_node *pred = get_Proj_pred(irn);
-static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
-{
- ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
- be_abi_call_flags_t fl = be_abi_call_get_flags(call);
- env->flags = fl.bits;
- env->irg = irg;
- env->aenv = aenv;
- env->isa = aenv->isa;
- return env;
+ if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
+ return 4;
+ if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
+ return -4;
+ }
+
+ return 0;
}
/**
*/
static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
+ ia32_abi_env_t *env = self;
- if (!env->flags.try_omit_fp) {
- int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
- ir_node *bl = get_irg_start_block(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ if (! env->flags.try_omit_fp) {
+ ir_node *bl = get_irg_start_block(env->irg);
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *push;
/* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
+ push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
*mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
*/
static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
{
- ia32_abi_env_t *env = self;
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ia32_abi_env_t *env = self;
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
if (env->flags.try_omit_fp) {
/* simply remove the stack frame here */
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
+ add_irn_dep(curr_sp, *mem);
}
else {
- const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
- ir_mode *mode_bp = env->isa->bp->reg_class->mode;
- int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
+ const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
+ ir_mode *mode_bp = env->isa->bp->reg_class->mode;
/* gcc always emits a leave at the end of a routine */
if (1 || ARCH_AMD(isa->opt_arch)) {
ir_node *leave;
/* leave */
- leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
+ leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
set_ia32_flags(leave, arch_irn_flags_ignore);
curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
*mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
}
else {
+ ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
ir_node *pop;
/* copy ebp to esp */
curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
/* pop ebp */
- pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
+ pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
set_ia32_flags(pop, arch_irn_flags_ignore);
curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
}
+/**
+ * Initialize the callback object.
+ * @param call The call object.
+ * @param aenv The architecture environment.
+ * @param irg The graph with the method.
+ * @return Some pointer. This pointer is passed to all other callback functions as self object.
+ */
+static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
+{
+ ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ env->flags = fl.bits;
+ env->irg = irg;
+ env->aenv = aenv;
+ env->isa = aenv->isa;
+ return env;
+}
+
+/**
+ * Destroy the callback object.
+ * @param self The callback object.
+ */
+static void ia32_abi_done(void *self) {
+ free(self);
+}
+
/**
* Produces the type which sits between the stack args and the locals on the stack.
* it will contain the return address and space to store the old base pointer.
static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
{
int cost;
- switch (get_ia32_irn_opcode(irn)) {
- case iro_ia32_xDiv:
- case iro_ia32_DivMod:
- cost = 8;
- break;
-
- case iro_ia32_xLoad:
- case iro_ia32_l_Load:
- case iro_ia32_Load:
- cost = 25;
- break;
-
- case iro_ia32_Push:
- case iro_ia32_Pop:
- cost = 5;
- break;
-
- case iro_ia32_xStore:
- case iro_ia32_l_Store:
- case iro_ia32_Store:
- case iro_ia32_Store8Bit:
- cost = 50;
- break;
-
- case iro_ia32_MulS:
- case iro_ia32_Mul:
- case iro_ia32_Mulh:
- case iro_ia32_xMul:
- case iro_ia32_l_MulS:
- case iro_ia32_l_Mul:
- cost = 2;
- break;
-
- default:
- cost = 1;
+ ia32_op_type_t op_tp;
+ const ia32_irn_ops_t *ops = self;
+
+ if (is_Proj(irn))
+ return 0;
+
+ assert(is_ia32_irn(irn));
+
+ cost = get_ia32_latency(irn);
+ op_tp = get_ia32_op_type(irn);
+
+ if (is_ia32_CopyB(irn)) {
+ cost = 250;
+ if (ARCH_INTEL(ops->cg->arch))
+ cost += 150;
+ }
+ else if (is_ia32_CopyB_i(irn)) {
+ int size = get_tarval_long(get_ia32_Immop_tarval(irn));
+ cost = 20 + (int)ceil((4/3) * size);
+ if (ARCH_INTEL(ops->cg->arch))
+ cost += 150;
+ }
+ /* in case of address mode operations add additional cycles */
+ else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
+ /*
+ In case of stack access add 5 cycles (we assume stack is in cache),
+ other memory operations cost 20 cycles.
+ */
+ cost += is_ia32_use_frame(irn) ? 5 : 20;
}
return cost;
}
else {
/* normal add: inverse == sub */
- ir_node *proj = get_irn_out_edge_first(irn)->src;
- assert(proj && is_Proj(proj));
+ ir_node *proj = ia32_get_res_proj(irn);
+ assert(proj);
inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
pnc = pn_ia32_Sub_res;
}
else {
/* normal sub */
- ir_node *proj = get_irn_out_edge_first(irn)->src;
- assert(proj && is_Proj(proj));
+ ir_node *proj = ia32_get_res_proj(irn);
+ assert(proj);
if (i == 2) {
inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
}
break;
case iro_ia32_Not: {
- ir_node *proj = get_irn_out_edge_first(irn)->src;
- assert(proj && is_Proj(proj));
+ ir_node *proj = ia32_get_res_proj(irn);
+ assert(proj);
inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
pnc = pn_ia32_Not_res;
inverse->costs += 1;
break;
}
- case iro_ia32_Minus:
- ir_node *proj = get_irn_out_edge_first(irn)->src;
- assert(proj && is_Proj(proj));
+ case iro_ia32_Minus: {
+ ir_node *proj = ia32_get_res_proj(irn);
+ assert(proj);
inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
- pnc = pn_ia32_Minus_res;
+ pnc = pn_ia32_Minus_res;
inverse->costs += 1;
break;
+ }
default:
/* inverse operation not supported */
return NULL;
return inverse;
}
+/**
+ * Check if irn can load it's operand at position i from memory (source addressmode).
+ * @param self Pointer to irn ops itself
+ * @param irn The irn to be checked
+ * @param i The operands position
+ * @return Non-Zero if operand can be loaded
+ */
+static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
+ if (! is_ia32_irn(irn) || /* must be an ia32 irn */
+ get_irn_arity(irn) != 5 || /* must be a binary operation */
+ get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
+ ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
+ (i != 2 && i != 3) || /* a "real" operand position must be requested */
+ (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
+ is_ia32_use_frame(irn)) /* must not already use frame */
+ return 0;
+
+ return 1;
+}
+
+static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
+ const ia32_irn_ops_t *ops = self;
+ ia32_code_gen_t *cg = ops->cg;
+
+ assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
+
+ if (i == 2) {
+ ir_node *tmp = get_irn_n(irn, 3);
+ set_irn_n(irn, 3, get_irn_n(irn, 2));
+ set_irn_n(irn, 2, tmp);
+ }
+
+ set_ia32_am_support(irn, ia32_am_Source);
+ set_ia32_op_type(irn, ia32_AddrModeS);
+ set_ia32_am_flavour(irn, ia32_B);
+ set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
+ set_ia32_use_frame(irn);
+ set_ia32_got_reload(irn);
+
+ set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
+ set_irn_n(irn, 4, spill);
+
+ /*
+ Input at position one is index register, which is NoReg.
+ We would need cg object to get a real noreg, but we cannot
+ access it from here.
+ */
+ set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
+
+ //FIXME DBG_OPT_AM_S(reload, irn);
+}
+
static const be_abi_callbacks_t ia32_abi_callbacks = {
ia32_abi_init,
- free,
+ ia32_abi_done,
ia32_abi_get_between_type,
ia32_abi_dont_save_regs,
ia32_abi_prologue,
ia32_classify,
ia32_get_flags,
ia32_get_frame_entity,
- ia32_set_stack_bias,
+ ia32_set_frame_entity,
+ ia32_set_frame_offset,
+ ia32_get_sp_bias,
ia32_get_inverse,
- ia32_get_op_estimated_cost
+ ia32_get_op_estimated_cost,
+ ia32_possible_memory_operand,
+ ia32_perform_memory_operand,
};
ia32_irn_ops_t ia32_irn_ops = {
* |___/
**************************************************/
+static void ia32_kill_convs(ia32_code_gen_t *cg) {
+ ir_node *irn;
+
+ /* BEWARE: the Projs are inserted in the set */
+ foreach_nodeset(cg->kill_conv, irn) {
+ ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
+ edges_reroute(irn, in, cg->birg->irg);
+ }
+}
+
+/**
+ * Transform the Thread Local Store base.
+ */
+static void transform_tls(ir_graph *irg) {
+ ir_node *irn = get_irg_tls(irg);
+
+ if (irn) {
+ dbg_info *dbg = get_irn_dbg_info(irn);
+ ir_node *blk = get_nodes_block(irn);
+ ir_node *newn;
+ newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
+
+ exchange(irn, newn);
+ }
+}
+
/**
* Transforms the standard firm graph into
* an ia32 firm graph
/* 2nd: transform all remaining nodes */
ia32_register_transformers();
dom = be_compute_dominance_frontiers(cg->irg);
+
+ cg->kill_conv = new_nodeset(5);
+ transform_tls(cg->irg);
irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
+ ia32_kill_convs(cg);
+ del_nodeset(cg->kill_conv);
+
be_free_dominance_frontiers(dom);
if (cg->dump)
}
static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
- int i;
+ int i, arity;
ir_mode *mode;
- ir_node *mem_proj;
+ ir_node *mem_proj = NULL;
if (is_Block(irn))
return;
mode = get_irn_mode(irn);
/* check if we already saw this node or the node has more than one user */
- if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
+ if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
return;
+ };
/* mark irn visited */
bitset_add_irn(already_visited, irn);
/* non-Tuple nodes with one user: ok, return */
- if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
+ if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
return;
+ }
/* tuple node has one user which is not the mem proj-> ok */
if (mode == mode_T && get_irn_n_edges(irn) == 1) {
- mem_proj = get_proj_for_mode(irn, mode_M);
- if (! mem_proj)
+ mem_proj = ia32_get_proj_for_mode(irn, mode_M);
+ if (mem_proj == NULL) {
return;
+ }
}
- for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
+ arity = get_irn_arity(irn);
+ for (i = 0; i < arity; ++i) {
ir_node *pred = get_irn_n(irn, i);
/* do not follow memory edges or we will accidentally remove stores */
- if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
+ if (get_irn_mode(pred) == mode_M) {
+ if(mem_proj != NULL) {
+ edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
+ mem_proj = NULL;
+ }
continue;
+ }
set_irn_n(irn, i, new_Bad());
remove_unused_nodes(pred, already_visited);
}
- if (sched_is_scheduled(irn))
+ // we need to set the presd to Bad again to also get the memory edges
+ arity = get_irn_arity(irn);
+ for (i = 0; i < arity; ++i) {
+ set_irn_n(irn, i, new_Bad());
+ }
+
+ if (sched_is_scheduled(irn)) {
sched_remove(irn);
+ }
}
static void remove_unused_loads_walker(ir_node *irn, void *env) {
*/
static void ia32_before_ra(void *self) {
ia32_code_gen_t *cg = self;
- bitset_t *already_visited = bitset_irg_malloc(cg->irg);
-
- cg->blk_sched = sched_create_block_schedule(cg->irg);
+ bitset_t *already_visited = bitset_irg_alloca(cg->irg);
/*
Handle special case:
We need to remove those Loads and all other nodes which won't be used
after removing the Load from schedule.
*/
- irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
- bitset_free(already_visited);
+ irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
}
else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
- else {
+ else
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
- }
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
DBG_OPT_RELOAD2LD(irn, new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
exchange(irn, proj);
}
+static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *frame = get_irg_frame(env->irg);
+
+ ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
+
+ set_ia32_frame_ent(push, ent);
+ set_ia32_use_frame(push);
+ set_ia32_op_type(push, ia32_AddrModeS);
+ set_ia32_am_flavour(push, ia32_B);
+ set_ia32_ls_mode(push, mode_Is);
+
+ sched_add_before(schedpoint, push);
+ return push;
+}
+
+static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *frame = get_irg_frame(env->irg);
+
+ ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
+
+ set_ia32_frame_ent(pop, ent);
+ set_ia32_use_frame(pop);
+ set_ia32_op_type(pop, ia32_AddrModeD);
+ set_ia32_am_flavour(pop, ia32_B);
+ set_ia32_ls_mode(pop, mode_Is);
+
+ sched_add_before(schedpoint, pop);
+
+ return pop;
+}
+
+static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
+ ir_mode *spmode = mode_Iu;
+ const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
+ ir_node *sp;
+
+ sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
+ arch_set_irn_register(env->cg->arch_env, sp, spreg);
+ sched_add_before(schedpoint, sp);
+
+ return sp;
+}
+
+/**
+ * Transform memperm, currently we do this the ugly way and produce
+ * push/pop into/from memory cascades. This is possible without using
+ * any registers.
+ */
+static void transform_MemPerm(ia32_transform_env_t *env) {
+ ir_node *node = env->irn;
+ int i, arity;
+ ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
+ const ir_edge_t *edge;
+ const ir_edge_t *next;
+ ir_node **pops;
+
+ arity = be_get_MemPerm_entity_arity(node);
+ pops = alloca(arity * sizeof(pops[0]));
+
+ // create pushs
+ for(i = 0; i < arity; ++i) {
+ entity *ent = be_get_MemPerm_in_entity(node, i);
+ ir_type *enttype = get_entity_type(ent);
+ int entbits = get_type_size_bits(enttype);
+ ir_node *mem = get_irn_n(node, i + 1);
+ ir_node *push;
+
+ assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+
+ push = create_push(env, node, sp, mem, ent);
+ sp = create_spproj(env, push, 0, node);
+ if(entbits == 64) {
+ // add another push after the first one
+ push = create_push(env, node, sp, mem, ent);
+ add_ia32_am_offs_int(push, 4);
+ sp = create_spproj(env, push, 0, node);
+ }
+
+ set_irn_n(node, i, new_Bad());
+ }
+
+ // create pops
+ for(i = arity - 1; i >= 0; --i) {
+ entity *ent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(ent);
+ int entbits = get_type_size_bits(enttype);
+
+ ir_node *pop;
+
+ assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+
+ pop = create_pop(env, node, sp, ent);
+ if(entbits == 64) {
+ // add another pop after the first one
+ sp = create_spproj(env, pop, 1, node);
+ pop = create_pop(env, node, sp, ent);
+ add_ia32_am_offs_int(pop, 4);
+ }
+ sp = create_spproj(env, pop, 1, node);
+
+ pops[i] = pop;
+ }
+
+ // exchange memprojs
+ foreach_out_edge_safe(node, edge, next) {
+ ir_node *proj = get_edge_src_irn(edge);
+ int p = get_Proj_proj(proj);
+
+ assert(p < arity);
+
+ set_Proj_pred(proj, pops[p]);
+ set_Proj_proj(proj, 3);
+ }
+
+ // remove memperm
+ arity = get_irn_arity(node);
+ for(i = 0; i < arity; ++i) {
+ set_irn_n(node, i, new_Bad());
+ }
+ sched_remove(node);
+}
+
/**
* Fix the mode of Spill/Reload
*/
transform_to_Load(&tenv);
}
else if (be_is_Spill(node)) {
+ ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
/* we always spill the whole register */
tenv.dbg = get_irn_dbg_info(node);
tenv.irn = node;
- tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
+ tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
transform_to_Store(&tenv);
}
+ else if(be_is_MemPerm(node)) {
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irn = node;
+ transform_MemPerm(&tenv);
+ }
}
}
*/
static void ia32_after_ra(void *self) {
ia32_code_gen_t *cg = self;
- irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
+ ir_graph *irg = cg->irg;
+
+ irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
+
+ ia32_finish_irg(irg, cg);
+}
+
+/**
+ * Last touchups for the graph before emit
+ */
+static void ia32_finish(void *self) {
+ ia32_code_gen_t *cg = self;
+ ir_graph *irg = cg->irg;
+
+ //be_remove_empty_blocks(irg);
+ cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
+
+ //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
/* if we do x87 code generation, rewrite all the virtual instructions and registers */
if (cg->used_fp == fp_x87 || cg->force_sim) {
- x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
+ x87_simulate_graph(cg->arch_env, irg, cg->blk_sched);
}
-}
+ ia32_peephole_optimization(irg, cg);
+}
/**
* Emits the code, closes the output file and frees
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- ia32_finish_irg(irg, cg);
- if (cg->dump)
- be_dump(irg, "-finished", dump_ir_block_graph_sched);
ia32_gen_routine(cg->isa->out, irg, cg);
cur_reg_set = NULL;
/* de-allocate code generator */
del_set(cg->reg_set);
- free(self);
-
+ free(cg);
}
static void *ia32_cg_init(const be_irg_t *birg);
ia32_before_sched, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
ia32_after_ra, /* after register allocation hook */
+ ia32_finish, /* called before codegen */
ia32_codegen /* emit && done */
};
};
/*
-* set the tarval output mode to C-semantics
-*/
+ * set the tarval output mode of all integer modes to decimal
+ */
static void set_tarval_output_modes(void)
{
- set_tarval_mode_output_option(get_modeLs(), &mo_integer);
- set_tarval_mode_output_option(get_modeLu(), &mo_integer);
- set_tarval_mode_output_option(get_modeIs(), &mo_integer);
- set_tarval_mode_output_option(get_modeIu(), &mo_integer);
- set_tarval_mode_output_option(get_modeHs(), &mo_integer);
- set_tarval_mode_output_option(get_modeHu(), &mo_integer);
- set_tarval_mode_output_option(get_modeBs(), &mo_integer);
- set_tarval_mode_output_option(get_modeBu(), &mo_integer);
- set_tarval_mode_output_option(get_modeC(), &mo_integer);
- set_tarval_mode_output_option(get_modeU(), &mo_integer);
- set_tarval_mode_output_option(get_modeIu(), &mo_integer);
+ int i;
+
+ for (i = get_irp_n_modes() - 1; i >= 0; --i) {
+ ir_mode *mode = get_irp_mode(i);
+
+ if (mode_is_int(mode))
+ set_tarval_mode_output_option(mode, &mo_integer);
+ }
}
&ia32_gp_regs[REG_ESP], /* stack pointer register */
&ia32_gp_regs[REG_EBP], /* base pointer register */
-1, /* stack direction */
+ NULL, /* main environment */
},
NULL, /* 16bit register names */
NULL, /* 8bit register names */
arch_pentium_4, /* optimize for architecture */
fp_sse2, /* use sse2 unit */
NULL, /* current code generator */
+ NULL, /* output file */
#ifndef NDEBUG
NULL, /* name obstack */
0 /* name obst size */
#endif /* NDEBUG */
ia32_handle_intrinsics();
- ia32_switch_section(NULL, NO_SECTION);
+ ia32_switch_section(isa->out, NO_SECTION);
fprintf(isa->out, "\t.intel_syntax\n");
+ /* needed for the debug support */
+ ia32_switch_section(isa->out, SECTION_TEXT);
+ fprintf(isa->out, ".Ltext0:\n");
+
inited = 1;
return isa;
ia32_isa_t *isa = self;
/* emit now all global declarations */
- ia32_gen_decls(isa->out);
+ ia32_gen_decls(isa->out, isa->arch_isa.main_env);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
* Return the register class for index i.
*/
static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
- const ia32_isa_t *isa = self;
assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
if (i == 0)
return &ia32_reg_classes[CLASS_ia32_gp];
/* set stack parameters */
for (i = stack_idx; i < n; i++) {
- be_abi_call_param_stack(abi, i, 1, 0, 0);
+ /* parameters on the stack are 32 bit aligned */
+ be_abi_call_param_stack(abi, i, 4, 0, 0);
}
tp = get_method_res_type(method_type, 1);
mode = get_type_mode(tp);
- assert(!mode_is_float(mode) && "two FP results not supported");
+ assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- reg = mode_is_float(mode) ?
- (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
- &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
be_abi_call_res_reg(abi, 0, reg);
}
return &ia32_code_gen_if;
}
+/**
+ * Returns the estimated execution time of an ia32 irn.
+ */
+static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
+ const arch_env_t *arch_env = env;
+ return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
+}
+
list_sched_selector_t ia32_sched_selector;
/**
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
-static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
-// memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
- memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
+static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
+ memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
+ ia32_sched_selector.exectime = ia32_sched_exectime;
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
projects / libfirm / blobdiff