#include "../be_t.h"
#include "../beirgmod.h"
#include "../be_dbgout.h"
+#include "../beblocksched.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
}
+/**
+ * Returns gp_noreg or fp_noreg, depending in input requirements.
+ */
+ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
+ arch_register_req_t req;
+ const arch_register_req_t *p_req;
+
+ p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
+ assert(p_req && "Missing register requirements");
+ if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
+ return ia32_new_NoReg_gp(cg);
+ else
+ return ia32_new_NoReg_fp(cg);
+}
+
/**************************************************
* _ _ _ __
* | | | (_)/ _|
return NULL;
}
- if (pos == -1) {
- node_pos = ia32_translate_proj_pos(irn);
- }
- else {
- node_pos = pos;
- }
-
- irn = skip_Proj(irn);
+ node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
+ irn = skip_Proj(irn);
DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
}
if (is_ia32_irn(irn)) {
- if (pos >= 0) {
- irn_req = get_ia32_in_req(irn, pos);
- }
- else {
- irn_req = get_ia32_out_req(irn, node_pos);
+ irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
+ if (irn_req == NULL) {
+ /* no requirements */
+ return NULL;
}
DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
if (is_Proj(irn)) {
- pos = ia32_translate_proj_pos(irn);
+ pos = get_Proj_proj(irn);
irn = skip_Proj(irn);
}
return NULL;
}
- pos = ia32_translate_proj_pos(irn);
+ pos = get_Proj_proj(irn);
irn = skip_Proj(irn);
}
}
static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
+ arch_irn_flags_t flags;
+ ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
- if(is_Proj(irn)) {
- ir_node *pred = get_Proj_pred(irn);
- int ia32_op = get_ia32_irn_opcode(pred);
- long proj = get_Proj_proj(irn);
- if (iro_ia32_Push == ia32_op && proj == pn_ia32_Push_stack) {
- /* Push modifies always ESP, this cannot be changed */
- return arch_irn_flags_modify_sp | arch_irn_flags_ignore;
- }
- if (iro_ia32_Pop == ia32_op && proj == pn_ia32_Pop_stack) {
- /* Pop modifies always ESP, this cannot be changed */
- return arch_irn_flags_modify_sp | arch_irn_flags_ignore;
- }
- if (iro_ia32_AddSP == ia32_op && proj == pn_ia32_AddSP_stack) {
- /* AddSP modifies always ESP, this cannot be changed */
- return arch_irn_flags_modify_sp | arch_irn_flags_ignore;
- }
- if (iro_ia32_SubSP == ia32_op && proj == pn_ia32_SubSP_stack) {
- /* SubSP modifies always ESP, this cannot be changed */
- return arch_irn_flags_modify_sp | arch_irn_flags_ignore;
- }
- }
-
- irn = skip_Proj(irn);
- if (is_ia32_irn(irn))
- return get_ia32_flags(irn);
+ if (is_Unknown(irn))
+ flags = arch_irn_flags_ignore;
else {
- if (is_Unknown(irn))
- return arch_irn_flags_ignore;
- return 0;
+ /* pred is only set, if we have a Proj */
+ flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
+
+ irn = skip_Proj(irn);
+ if (is_ia32_irn(irn))
+ flags |= get_ia32_flags(irn);
}
+
+ return flags;
}
/**
}
static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
+ const ia32_irn_ops_t *ops = self;
+ ia32_code_gen_t *cg = ops->cg;
+
assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
if (i == 2) {
set_ia32_op_type(irn, ia32_AddrModeS);
set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
- //TODO this will fail, if spill is a PhiM (give PhiMs entities?)
- set_ia32_frame_ent(irn, be_get_frame_entity(spill));
set_ia32_use_frame(irn);
set_ia32_got_reload(irn);
We would need cg object to get a real noreg, but we cannot
access it from here.
*/
- set_irn_n(irn, 3, get_irn_n(irn, 1));
+ set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
//FIXME DBG_OPT_AM_S(reload, irn);
}
else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
}
- else {
+ else
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
- }
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
DBG_OPT_RELOAD2LD(irn, new_op);
- proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
if (sched_point) {
sched_add_after(sched_point, new_op);
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- // Matze: disabled for now, as the irextbb algo sometimes returns extbb in
- // the wrong order if the graph has critical edges
- be_remove_empty_blocks(irg);
+ //be_remove_empty_blocks(irg);
+ cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
- cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
+ //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
/* if we do x87 code generation, rewrite all the virtual instructions and registers */
if (cg->used_fp == fp_x87 || cg->force_sim) {
tp = get_method_res_type(method_type, 1);
mode = get_type_mode(tp);
- assert(!mode_is_float(mode) && "two FP results not supported");
+ assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- reg = mode_is_float(mode) ?
- (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
- &ia32_gp_regs[REG_EAX];
+ reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
be_abi_call_res_reg(abi, 0, reg);
}
projects / libfirm / blobdiff