don't aggressively fold some nodes when we know it will increase register pressure

[libfirm] / ir / be / ia32 / bearch_ia32.c

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index bb7e0c8..2df1483 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -633,7 +633,7 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
                        cost += 150;
        }
        else if (is_ia32_CopyB_i(irn)) {
-               int size = get_ia32_pncode(irn);
+               int size = get_ia32_copyb_size(irn);
                cost     = 20 + (int)ceil((4/3) * size);
                if (ARCH_INTEL(ops->cg->arch))
                        cost += 150;
@@ -906,7 +906,7 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = {
        ia32_perform_memory_operand,
 };
 
-ia32_irn_ops_t ia32_irn_ops = {
+static ia32_irn_ops_t ia32_irn_ops = {
        &ia32_irn_ops_if,
        NULL
 };
@@ -925,9 +925,14 @@ ia32_irn_ops_t ia32_irn_ops = {
  **************************************************/
 
 static void ia32_before_abi(void *self) {
+       lower_mode_b_config_t lower_mode_b_config = {
+               mode_Iu,  /* lowered mode */
+               mode_Bu,  /* prefered mode for set */
+               0,        /* don't lower direct compares */
+       };
        ia32_code_gen_t *cg = self;
 
-       ir_lower_mode_b(cg->irg, mode_Iu, 0);
+       ir_lower_mode_b(cg->irg, &lower_mode_b_config);
        if(cg->dump)
                be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
 }
@@ -1346,7 +1351,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
        }
 
        in[0] = sp;
-       keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+       keep  = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
        sched_add_before(node, keep);
 
        // exchange memprojs
@@ -1416,12 +1421,13 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
                        be_node_needs_frame_entity(env, node, mode, align);
                } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
                           || is_ia32_vfld(node)) {
-                       const ir_mode *mode = get_ia32_ls_mode(node);
-                       int align = 4;
+                       const ir_mode *mode  = get_ia32_ls_mode(node);
+                       int            align = 4;
                        be_node_needs_frame_entity(env, node, mode, align);
                } else if(is_ia32_FldCW(node)) {
-                       const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
-                       int align = 4;
+                       /* although 2 byte would be enough 4 byte performs best */
+                       const ir_mode *mode  = mode_Iu;
+                       int            align = 4;
                        be_node_needs_frame_entity(env, node, mode, align);
                } else {
 #ifndef NDEBUG
@@ -2320,6 +2326,7 @@ static const lc_opt_table_entry_t ia32_options[] = {
        LC_OPT_ENT_ENUM_INT("opt",       "optimize for instruction architecture", &opt_arch_var),
        LC_OPT_ENT_ENUM_INT("fpunit",    "select the floating point unit", &fp_unit_var),
        LC_OPT_ENT_NEGBIT("nooptcc",  "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
+       LC_OPT_ENT_BIT("unsafe_floatconv",  "do unsage floating point controlword optimisations", &ia32_isa_template.opt, IA32_OPT_UNSAFE_FLOATCONV),
        LC_OPT_ENT_ENUM_INT("gasmode",   "set the GAS compatibility mode", &gas_var),
        LC_OPT_LAST
 };