#include "irgopt.h"
#include "irbitset.h"
#include "pdeq.h"
+#include "pset.h"
#include "debug.h"
#include "../beabi.h" /* the general register allocator interface */
#include "../beirgmod.h"
#include "../be_dbgout.h"
#include "../beblocksched.h"
+#include "../bemachine.h"
+#include "../beilpsched.h"
+
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "gen_ia32_machine.h"
#include "ia32_gen_decls.h" /* interface declaration emitter */
#include "ia32_transform.h"
#include "ia32_emitter.h"
ia32_abi_env_t *env = self;
- if ( !between_type) {
+ if (! between_type) {
entity *old_bp_ent;
entity *ret_addr_ent;
entity *omit_fp_ret_addr_ent;
const ia32_irn_ops_t *ops = self;
if (is_Proj(irn))
- return 0;
+ return 0;
+ if (!is_ia32_irn(irn))
+ return 0;
assert(is_ia32_irn(irn));
cg->kill_conv = new_nodeset(5);
transform_tls(cg->irg);
+ edges_deactivate(cg->irg);
+ edges_activate(cg->irg);
irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
ia32_kill_convs(cg);
del_nodeset(cg->kill_conv);
isa->cg = cg;
#ifndef NDEBUG
- if (isa->name_obst_size) {
- //printf("freed %d bytes from name obst\n", isa->name_obst_size);
- isa->name_obst_size = 0;
+ if (isa->name_obst) {
obstack_free(isa->name_obst, NULL);
obstack_init(isa->name_obst);
}
NULL, /* types */
NULL, /* tv_ents */
(0 |
- IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
- IA32_OPT_DOAM | /* optimize address mode default: on */
- IA32_OPT_LEA | /* optimize for LEAs default: on */
- IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
- IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
- IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
+ IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
+ IA32_OPT_DOAM | /* optimize address mode default: on */
+ IA32_OPT_LEA | /* optimize for LEAs default: on */
+ IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
+ IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
+ IA32_OPT_EXTBB | /* use extended basic block scheduling, default: on */
+ IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
arch_pentium_4, /* instruction architecture */
arch_pentium_4, /* optimize for architecture */
fp_sse2, /* use sse2 unit */
isa->types = pmap_create();
isa->tv_ent = pmap_create();
isa->out = file_handle;
+ isa->cpu = ia32_init_machine_description();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
/* patch register names of x87 registers */
- if (USE_x87(isa)) {
- ia32_st_regs[0].name = "st";
- ia32_st_regs[1].name = "st(1)";
- ia32_st_regs[2].name = "st(2)";
- ia32_st_regs[3].name = "st(3)";
- ia32_st_regs[4].name = "st(4)";
- ia32_st_regs[5].name = "st(5)";
- ia32_st_regs[6].name = "st(6)";
- ia32_st_regs[7].name = "st(7)";
- }
+ ia32_st_regs[0].name = "st";
+ ia32_st_regs[1].name = "st(1)";
+ ia32_st_regs[2].name = "st(2)";
+ ia32_st_regs[3].name = "st(3)";
+ ia32_st_regs[4].name = "st(4)";
+ ia32_st_regs[5].name = "st(5)";
+ ia32_st_regs[6].name = "st(6)";
+ ia32_st_regs[7].name = "st(7)";
#ifndef NDEBUG
isa->name_obst = xmalloc(sizeof(*isa->name_obst));
obstack_init(isa->name_obst);
- isa->name_obst_size = 0;
#endif /* NDEBUG */
ia32_handle_intrinsics();
pmap_destroy(isa->types);
#ifndef NDEBUG
- //printf("name obst size = %d bytes\n", isa->name_obst_size);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
return &ia32_sched_selector;
}
+static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
+ return NULL;
+}
+
/**
* Returns the necessary byte alignment for storing a register of given class.
*/
return bytes;
}
-static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
+static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
+ static const be_execution_unit_t *_allowed_units_BRANCH[] = {
+ &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
+ &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
+ NULL,
+ };
+ static const be_execution_unit_t *_allowed_units_ALU[] = {
+ &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU1],
+ &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU2],
+ &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU3],
+ &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU4],
+ NULL,
+ };
+ static const be_execution_unit_t *_allowed_units_DUMMY[] = {
+ &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY1],
+ &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY2],
+ &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY3],
+ &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY4],
+ NULL,
+ };
+ static const be_execution_unit_t **_units_callret[] = {
+ _allowed_units_BRANCH,
+ NULL
+ };
+ static const be_execution_unit_t **_units_other[] = {
+ _allowed_units_ALU,
+ NULL
+ };
+ static const be_execution_unit_t **_units_dummy[] = {
+ _allowed_units_DUMMY,
+ NULL
+ };
+ const be_execution_unit_t ***ret;
+
+ if (is_ia32_irn(irn)) {
+ ret = get_ia32_exec_units(irn);
+ }
+ else if (is_be_node(irn)) {
+ if (be_is_Call(irn) || be_is_Return(irn)) {
+ ret = _units_callret;
+ }
+ else if (be_is_Barrier(irn)) {
+ ret = _units_dummy;
+ }
+ else {
+ ret = _units_other;
+ }
+ }
+ else {
+ ret = _units_dummy;
+ }
+
+ return ret;
+}
+
+/**
+ * Return the abstract ia32 machine.
+ */
+static const be_machine_t *ia32_get_machine(const void *self) {
+ const ia32_isa_t *isa = self;
+ return isa->cpu;
+}
+
+/**
+ * Allows or disallows the creation of Psi nodes for the given Phi nodes.
+ * @return 1 if allowed, 0 otherwise
+ */
+static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
+{
+ ir_node *cmp, *cmp_a, *phi;
+ ir_mode *mode;
+
+/* we don't want long long an floating point Psi */
+#define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
+
+ if (get_irn_mode(sel) != mode_b)
+ return 0;
+
+ cmp = get_Proj_pred(sel);
+ cmp_a = get_Cmp_left(cmp);
+ mode = get_irn_mode(cmp_a);
+
+ if (IS_BAD_PSI_MODE(mode))
+ return 0;
+
+ /* check the Phi nodes */
+ for (phi = phi_list; phi; phi = get_irn_link(phi)) {
+ ir_node *pred_i = get_irn_n(phi, i);
+ ir_node *pred_j = get_irn_n(phi, j);
+ ir_mode *mode_i = get_irn_mode(pred_i);
+ ir_mode *mode_j = get_irn_mode(pred_j);
+
+ if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
+ return 0;
+ }
+
+#undef IS_BAD_PSI_MODE
+
+ return 1;
+}
+
+static ia32_intrinsic_env_t intrinsic_env = {
+ NULL, /**< the irg, these entities belong to */
+ NULL, /**< entity for first div operand (move into FPU) */
+ NULL, /**< entity for second div operand (move into FPU) */
+ NULL, /**< entity for converts ll -> d */
+ NULL, /**< entity for converts d -> ll */
+};
/**
* Returns the libFirm configuration parameter for this backend.
*/
static const backend_params *ia32_get_libfirm_params(void) {
+ static const opt_if_conv_info_t ifconv = {
+ 4, /* maxdepth, doesn't matter for Psi-conversion */
+ ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
+ };
static const arch_dep_params_t ad = {
- 1, /* also use subs */
- 4, /* maximum shifts */
+ 1, /* also use subs */
+ 4, /* maximum shifts */
31, /* maximum shift amount */
- 1, /* allow Mulhs */
- 1, /* allow Mulus */
+ 1, /* allow Mulhs */
+ 1, /* allow Mulus */
32 /* Mulh allowed up to 32 bit */
};
static backend_params p = {
1, /* need dword lowering */
ia32_create_intrinsic_fkt,
&intrinsic_env, /* context for ia32_create_intrinsic_fkt */
+ NULL, /* will be set later */
};
- p.dep_param = &ad;
+ p.dep_param = &ad;
+ p.if_conv_info = &ifconv;
return &p;
}
#ifdef WITH_LIBCORE
LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
+ LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
{ NULL }
};
* ia32-noplacecnst do not place constants,
* ia32-noimmop no operations with immediates
* ia32-noextbb do not use extended basic block scheduling
+ * ia32-nopushargs do not create pushs for function argument passing
* ia32-gasmode set the GAS compatibility mode
*/
static void ia32_register_options(lc_opt_entry_t *ent)
ia32_get_irn_handler,
ia32_get_code_generator_if,
ia32_get_list_sched_selector,
+ ia32_get_ilp_sched_selector,
ia32_get_reg_class_alignment,
ia32_get_libfirm_params,
+ ia32_get_allowed_execution_units,
+ ia32_get_machine,
#ifdef WITH_LIBCORE
ia32_register_options
#endif
projects / libfirm / blobdiff