use own mode for fpcw, fix constants for shift, xmm const assembler

[libfirm] / ir / be / ia32 / bearch_ia32.c

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 67e52f7..2c24f29 100644 (file)
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -7,14 +7,6 @@
 #include "config.h"
 #endif
 
-#ifdef HAVE_MALLOC_H
-#include <malloc.h>
-#endif
-
-#ifdef HAVE_ALLOCA_H
-#include <alloca.h>
-#endif
-
 #include <libcore/lc_opts.h>
 #include <libcore/lc_opts_enum.h>
 
@@ -34,9 +26,10 @@
 #include "pset.h"
 #include "debug.h"
 #include "error.h"
+#include "xmalloc.h"
 
 #include "../beabi.h"
-#include "../beirg.h"
+#include "../beirg_t.h"
 #include "../benode_t.h"
 #include "../belower.h"
 #include "../besched_t.h"
@@ -72,11 +65,13 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 /* TODO: ugly */
 static set *cur_reg_set = NULL;
 
+ir_mode *mode_fpcw = NULL;
+
 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
 
 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
                                     create_const_node_func func,
-                                    arch_register_t* reg)
+                                    const arch_register_t* reg)
 {
        ir_node *block, *res;
 
@@ -1081,15 +1076,12 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
                        store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
                else
                        store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
-       }
-       else if (get_mode_size_bits(mode) == 128) {
+       } else if (get_mode_size_bits(mode) == 128) {
                // Spill 128 bit SSE registers
                store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
-       }
-       else if (get_mode_size_bits(mode) == 8) {
+       } else if (get_mode_size_bits(mode) == 8) {
                store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
-       }
-       else {
+       } else {
                store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
        }
 
@@ -1513,12 +1505,17 @@ static void *ia32_init(FILE *file_handle) {
 
        if (inited)
                return NULL;
+       inited = 1;
 
        set_tarval_output_modes();
 
        isa = xmalloc(sizeof(*isa));
        memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
+       if(mode_fpcw == NULL) {
+               mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+       }
+
        ia32_register_init(isa);
        ia32_create_opcodes();
        ia32_register_copy_attr_func();
@@ -1543,16 +1540,6 @@ static void *ia32_init(FILE *file_handle) {
        ia32_build_16bit_reg_map(isa->regs_16bit);
        ia32_build_8bit_reg_map(isa->regs_8bit);
 
-       /* patch register names of x87 registers */
-       ia32_st_regs[0].name = "st";
-       ia32_st_regs[1].name = "st(1)";
-       ia32_st_regs[2].name = "st(2)";
-       ia32_st_regs[3].name = "st(3)";
-       ia32_st_regs[4].name = "st(4)";
-       ia32_st_regs[5].name = "st(5)";
-       ia32_st_regs[6].name = "st(6)";
-       ia32_st_regs[7].name = "st(7)";
-
 #ifndef NDEBUG
        isa->name_obst = xmalloc(sizeof(*isa->name_obst));
        obstack_init(isa->name_obst);
@@ -1565,7 +1552,11 @@ static void *ia32_init(FILE *file_handle) {
        be_emit_cstring(&isa->emit, ".Ltext0:\n");
        be_emit_write_line(&isa->emit);
 
-       inited = 1;
+       /* we mark referenced global entities, so we can only emit those which
+        * are actually referenced. (Note: you mustn't use the type visited flag
+        * elsewhere in the backend)
+        */
+       inc_master_type_visited();
 
        return isa;
 }