* $Id$
*/
#ifdef HAVE_CONFIG_H
-#include <config.h>
+#include "config.h"
#endif
-#ifdef HAVE_MALLOC_H
-#include <malloc.h>
-#endif
-
-#ifdef HAVE_ALLOCA_H
-#include <alloca.h>
-#endif
-
-#ifdef WITH_LIBCORE
#include <libcore/lc_opts.h>
#include <libcore/lc_opts_enum.h>
-#endif /* WITH_LIBCORE */
#include <math.h>
#include "irgmod.h"
#include "irgopt.h"
#include "irbitset.h"
+#include "irgopt.h"
#include "pdeq.h"
#include "pset.h"
#include "debug.h"
+#include "error.h"
+#include "xmalloc.h"
-#include "../beabi.h" /* the general register allocator interface */
+#include "../beabi.h"
+#include "../beirg_t.h"
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
#include "../beilpsched.h"
#include "../bespillslots.h"
#include "../bemodule.h"
+#include "../begnuas.h"
+#include "../bestate.h"
#include "bearch_ia32_t.h"
-#include "ia32_new_nodes.h" /* ia32 nodes interface */
-#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "ia32_new_nodes.h"
+#include "gen_ia32_regalloc_if.h"
#include "gen_ia32_machine.h"
-#include "ia32_gen_decls.h" /* interface declaration emitter */
#include "ia32_transform.h"
#include "ia32_emitter.h"
#include "ia32_map_regs.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
#include "ia32_util.h"
+#include "ia32_fpu.h"
-#define DEBUG_MODULE "firm.be.ia32.isa"
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/* TODO: ugly */
static set *cur_reg_set = NULL;
+ir_mode *mode_fpcw = NULL;
+
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
- create_const_node_func func, arch_register_t* reg)
+ create_const_node_func func,
+ const arch_register_t* reg)
{
ir_node *block, *res;
- ir_node *in[1];
- ir_node *startnode;
- ir_node *keep;
if(*place != NULL)
return *place;
arch_set_irn_register(cg->arch_env, res, reg);
*place = res;
+#if 0
/* keep the node so it isn't accidently removed when unused ... */
in[0] = res;
keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
-
- /* schedule the node if we already have a scheduled program */
- startnode = get_irg_start(cg->irg);
- if(sched_is_scheduled(startnode)) {
- sched_add_after(startnode, res);
- sched_add_after(res, keep);
- }
+#endif
+ add_irn_dep(get_irg_end(cg->irg), res);
+ /* add_irn_dep(get_irg_start(cg->irg), res); */
return res;
}
&ia32_xmm_regs[REG_XMM_UKNWN]);
}
+ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
+ return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
+ &ia32_fp_cw_regs[REG_FPCW]);
+}
+
/**
* Returns gp_noreg or fp_noreg, depending in input requirements.
*/
ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
- arch_register_req_t req;
- const arch_register_req_t *p_req;
+ const arch_register_req_t *req;
- p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
- assert(p_req && "Missing register requirements");
- if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
+ req = arch_get_register_req(cg->arch_env, irn, pos);
+ assert(req != NULL && "Missing register requirements");
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
return ia32_new_NoReg_gp(cg);
- else
- return ia32_new_NoReg_fp(cg);
+
+ return ia32_new_NoReg_fp(cg);
}
/**************************************************
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const ia32_irn_ops_t *ops = self;
- const ia32_register_req_t *irn_req;
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
- FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
-
- if (is_Block(irn) || mode == mode_X) {
- DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
- return NULL;
+static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
+ const ir_node *node,
+ int pos) {
+ long node_pos = pos == -1 ? 0 : pos;
+ ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
+
+ if (is_Block(node) || mode == mode_X) {
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
- return NULL;
+ return arch_no_register_req;
}
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
- if (is_Proj(irn)) {
+ if (is_Proj(node)) {
if(mode == mode_M)
- return NULL;
+ return arch_no_register_req;
if(pos >= 0) {
- DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
- return NULL;
+ return arch_no_register_req;
}
- node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
- irn = skip_Proj_const(irn);
-
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
+ node = skip_Proj_const(node);
}
- if (is_ia32_irn(irn)) {
- irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
- if (irn_req == NULL) {
- /* no requirements */
- return NULL;
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
+ if (is_ia32_irn(node)) {
+ const arch_register_req_t *req;
+ if(pos >= 0)
+ req = get_ia32_in_req(node, pos);
+ else
+ req = get_ia32_out_req(node, node_pos);
- memcpy(req, &(irn_req->req), sizeof(*req));
+ assert(req != NULL);
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
- }
- else {
- /* treat Unknowns like Const with default requirements */
- if (is_Unknown(irn)) {
- DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- if (USE_SSE2(ops->cg))
- memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
- else
- memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode))
- memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
- return NULL;
- }
- else
- assert(0 && "unsupported Unknown-Mode");
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
- req = NULL;
- }
+ return req;
}
- return req;
+ /* unknowns should be transformed already */
+ assert(!is_Unknown(node));
+
+ return arch_no_register_req;
}
static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
int pos = 0;
- const ia32_irn_ops_t *ops = self;
if (get_irn_mode(irn) == mode_X) {
return;
}
- DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
-
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = skip_Proj(irn);
slots = get_ia32_slots(irn);
slots[pos] = reg;
- }
- else {
+ } else {
ia32_set_firm_reg(irn, reg, cur_reg_set);
}
}
const arch_register_t **slots;
slots = get_ia32_slots(irn);
reg = slots[pos];
- }
- else {
+ } else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
}
}
}
- DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
-
am_flav = get_ia32_am_flavour(irn);
am_flav |= ia32_O;
set_ia32_am_flavour(irn, am_flav);
pset_insert_ptr(s, env->isa->bp);
}
-#if 0
-static unsigned count_callee_saves(ia32_code_gen_t *cg)
-{
- unsigned callee_saves = 0;
- int c, num_reg_classes;
- arch_isa_if_t *isa;
-
- num_reg_classes = arch_isa_get_n_reg_class(isa);
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
- arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
-
- num_registers = arch_register_class_n_regs(regclass);
- for(r = 0; r < num_registers; ++r) {
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(arch_register_type_is(reg, callee_save))
- callee_saves++;
- }
- }
-
- return callee_saves;
-}
-
-static void create_callee_save_regprojs(ia32_code_gen_t *cg, ir_node *regparams)
-{
- int c, num_reg_classes;
- arch_isa_if_t *isa;
- long n = 0;
-
- num_reg_classes = arch_isa_get_n_reg_class(isa);
- cg->initial_regs = obstack_alloc(cg->obst,
- num_reg_classes * sizeof(cg->initial_regs[0]));
-
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
- ir_node **initial_regclass;
- arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
-
- num_registers = arch_register_class_n_regs(regclass);
- initial_regclass = obstack_alloc(num_registers * sizeof(initial_regclass[0]));
- for(r = 0; r < num_registers; ++r) {
- ir_node *proj;
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(!arch_register_type_is(reg, callee_save))
- continue;
-
- proj = new_r_Proj(irg, start_block, regparams, n);
- be_set_constr_single_reg(regparams, n, reg);
- arch_set_irn_register(cg->arch_env, proj, reg);
-
- initial_regclass[r] = proj;
- n++;
- }
- cg->initial_regs[c] = initial_regclass;
- }
-}
-
-static void callee_saves_obstack_grow(ia32_code_gen_t *cg)
-{
- int c, num_reg_classes;
- arch_isa_if_t *isa;
-
- for(c = 0; c < num_reg_classes; ++c) {
- int r, num_registers;
-
- num_registers = arch_register_class_n_regs(regclass);
- for(r = 0; r < num_registers; ++r) {
- ir_node *proj;
- arch_register_t *reg = arch_register_for_index(regclass, r);
- if(!arch_register_type_is(reg, callee_save))
- continue;
-
- proj = cg->initial_regs[c][r];
- obstack_ptr_grow(cg->obst, proj);
- }
- }
-}
-
-static unsigned count_parameters_in_regs(ia32_code_gen_t *cg)
-{
- return 0;
-}
-
-static void ia32_gen_prologue(ia32_code_gen_t *cg)
-{
- ir_graph *irg = cg->irg;
- ir_node *start_block = get_irg_start_block(irg);
- ir_node *sp;
- ir_node *regparams;
- int n_regparams_out;
-
- /* Create the regparams node */
- n_regparams_out = count_callee_saves(cg) + count_parameters_in_regs(cg);
- regparams = be_new_RegParams(irg, start_block, n_regparams_out);
-
- create_callee_save_regprojs(cg, regparams);
-
- /* Setup the stack */
- if(!omit_fp) {
- ir_node *bl = get_irg_start_block(env->irg);
- ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
- ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
- ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *push;
-
- /* push ebp */
- push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
- curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
- *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
-
- /* the push must have SP out register */
- arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
- set_ia32_flags(push, arch_irn_flags_ignore);
-
- /* move esp to ebp */
- curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
- be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
- arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
- be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- /* beware: the copy must be done before any other sp use */
- curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
- be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
- arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
- be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
-
- be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
- be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
- }
-
- sp = be_new_IncSP(sp, irg, start_block, initialsp, BE_STACK_FRAME_SIZE_EXPAND);
- set_irg_frame(irg, sp);
-}
-
-static void ia32_gen_epilogue(ia32_code_gen_t *cg)
-{
- int n_callee_saves = count_callee_saves(cg);
- int n_results_regs = 0;
- int barrier_size;
- ir_node *barrier;
- ir_node *end_block = get_irg_end_block(irg);
- ir_node **in;
-
- /* We have to make sure that all reloads occur before the stack frame
- gets destroyed, so we create a barrier for all callee-save and return
- values here */
- barrier_size = n_callee_saves + n_results_regs;
- barrier = be_new_Barrier(irg, end_block, barrier_size,
-
- /* simply remove the stack frame here */
- curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
- add_irn_dep(curr_sp, *mem);
-}
-#endif
-
/**
* Generate the routine prologue.
*
ia32_abi_get_between_type,
ia32_abi_dont_save_regs,
ia32_abi_prologue,
- ia32_abi_epilogue,
+ ia32_abi_epilogue
};
/* fill register allocator interface */
*/
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
-
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
- /* 1st: transform psi condition trees */
+ /* transform psi condition trees */
ia32_pre_transform_phase(cg);
- /* 2nd: transform all remaining nodes */
+ /* transform all remaining nodes */
ia32_transform_graph(cg);
+ //add_fpu_edges(cg->birg);
+
// Matze: disabled for now. Because after transformation start block has no
// self-loop anymore so it might be merged with its successor block. This
// will bring several nodes to the startblock which sometimes get scheduled
// before the initial IncSP/Barrier
- //local_optimize_graph(cg->irg);
+ local_optimize_graph(cg->irg);
if (cg->dump)
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
- /* 3rd: optimize address mode */
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
+ /* optimize address mode */
ia32_optimize_addressmode(cg);
if (cg->dump)
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
- DEBUG_ONLY(cg->mod = old_mod;)
+ /* do code placement, to optimize the position of constants */
+ place_code(cg->irg);
+
+ if (cg->dump)
+ be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
}
/**
after removing the Load from schedule.
*/
irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
+
+ /* setup fpu rounding modes */
+ ia32_setup_fpu_mode(cg);
}
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
}
+ else if (get_mode_size_bits(spillmode) == 128) {
+ // Reload 128 bit sse registers
+ new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
+ }
else
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
sched_point = sched_prev(node);
}
+ /* No need to spill unknown values... */
+ if(is_ia32_Unknown_GP(val) ||
+ is_ia32_Unknown_VFP(val) ||
+ is_ia32_Unknown_XMM(val)) {
+ store = nomem;
+ if(sched_point)
+ sched_remove(node);
+
+ exchange(node, store);
+ return;
+ }
+
if (mode_is_float(mode)) {
if (USE_SSE2(cg))
store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
else
store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else if (get_mode_size_bits(mode) == 8) {
+ } else if (get_mode_size_bits(mode) == 128) {
+ // Spill 128 bit SSE registers
+ store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
+ } else if (get_mode_size_bits(mode) == 8) {
store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else {
+ } else {
store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
}
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
-
- DBG_OPT_SPILL2ST(node, store);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
+ DBG_OPT_SPILL2ST(node, store);
if (sched_point) {
sched_add_after(sched_point, store);
const ir_mode *mode = get_ia32_ls_mode(node);
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
+ } else if(is_ia32_FldCW(node)) {
+ const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
+ int align = 4;
+ be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_SetST0(node)) {
const ir_mode *mode = get_ia32_ls_mode(node);
int align = 4;
&& !is_ia32_xStore(node)
&& !is_ia32_xStoreSimple(node)
&& !is_ia32_vfist(node)
- && !is_ia32_GetST0(node)) {
+ && !is_ia32_GetST0(node)
+ && !is_ia32_FnstCW(node)) {
assert(0);
}
#endif
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- ia32_gen_routine(cg, cg->isa->out, irg);
+ ia32_gen_routine(cg, irg);
cur_reg_set = NULL;
cg->used_fp = fp_none;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
-
/* copy optimizations from isa for easier access */
cg->opt = isa->opt;
cg->arch = isa->arch;
-1, /* stack direction */
NULL, /* main environment */
},
+ { NULL, }, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* types */
arch_pentium_4, /* optimize for architecture */
fp_sse2, /* use sse2 unit */
NULL, /* current code generator */
- NULL, /* output file */
#ifndef NDEBUG
NULL, /* name obstack */
0 /* name obst size */
if (inited)
return NULL;
+ inited = 1;
set_tarval_output_modes();
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ia32_isa_template, sizeof(*isa));
+ if(mode_fpcw == NULL) {
+ mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ }
+
ia32_register_init(isa);
ia32_create_opcodes();
ia32_register_copy_attr_func();
isa->opt &= ~IA32_OPT_INCDEC;
}
+ be_emit_init_env(&isa->emit, file_handle);
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
isa->types = pmap_create();
isa->tv_ent = pmap_create();
- isa->out = file_handle;
isa->cpu = ia32_init_machine_description();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
- /* patch register names of x87 registers */
- ia32_st_regs[0].name = "st";
- ia32_st_regs[1].name = "st(1)";
- ia32_st_regs[2].name = "st(2)";
- ia32_st_regs[3].name = "st(3)";
- ia32_st_regs[4].name = "st(4)";
- ia32_st_regs[5].name = "st(5)";
- ia32_st_regs[6].name = "st(6)";
- ia32_st_regs[7].name = "st(7)";
-
#ifndef NDEBUG
isa->name_obst = xmalloc(sizeof(*isa->name_obst));
obstack_init(isa->name_obst);
#endif /* NDEBUG */
ia32_handle_intrinsics();
- ia32_switch_section(isa->out, NO_SECTION);
/* needed for the debug support */
- ia32_switch_section(isa->out, SECTION_TEXT);
- fprintf(isa->out, ".Ltext0:\n");
+ be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
+ be_emit_cstring(&isa->emit, ".Ltext0:\n");
+ be_emit_write_line(&isa->emit);
- inited = 1;
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
return isa;
}
ia32_isa_t *isa = self;
/* emit now all global declarations */
- ia32_gen_decls(isa->out, isa->arch_isa.main_env);
+ be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
+ be_emit_destroy_env(&isa->emit);
+
free(self);
}
* - the general purpose registers
* - the SSE floating point register set
* - the virtual floating point registers
+ * - the SSE vector register set
*/
static int ia32_get_n_reg_class(const void *self) {
- return 3;
+ return N_CLASSES;
}
/**
* Return the register class for index i.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
- if (i == 0)
- return &ia32_reg_classes[CLASS_ia32_gp];
- else if (i == 1)
- return &ia32_reg_classes[CLASS_ia32_xmm];
- else
- return &ia32_reg_classes[CLASS_ia32_vfp];
+static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
+{
+ assert(i >= 0 && i < N_CLASSES);
+ return &ia32_reg_classes[i];
}
/**
}
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ia32_irn(irn) ? 1 : -1;
+ if(!is_ia32_irn(irn))
+ return -1;
+
+ if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
+ || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
+ || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn))
+ return 0;
+
+ return 1;
}
/**
p.if_conv_info = &ifconv;
return &p;
}
-#ifdef WITH_LIBCORE
/* instruction set architectures. */
static const lc_opt_enum_int_items_t arch_items[] = {
};
static const lc_opt_enum_int_items_t gas_items[] = {
- { "linux", ASM_LINUX_GAS },
- { "mingw", ASM_MINGW_GAS },
+ { "normal", GAS_FLAVOUR_NORMAL },
+ { "mingw", GAS_FLAVOUR_MINGW },
{ NULL, 0 }
};
static lc_opt_enum_int_var_t gas_var = {
- (int *)&asm_flavour, gas_items
+ (int*) &be_gas_flavour, gas_items
};
static const lc_opt_table_entry_t ia32_options[] = {
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
{ NULL }
};
-#endif /* WITH_LIBCORE */
const arch_isa_if_t ia32_isa_if = {
ia32_init,
ia32_get_irg_list,
};
+void ia32_init_emitter(void);
+void ia32_init_finish(void);
+void ia32_init_optimize(void);
+void ia32_init_transform(void);
+void ia32_init_x87(void);
+
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
+
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
+
+ ia32_init_emitter();
+ ia32_init_finish();
+ ia32_init_optimize();
+ ia32_init_transform();
+ ia32_init_x87();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
projects / libfirm / blobdiff