+/**
+ * This is the main ia32 firm backend driver.
+ *
+ * $Id$
+ */
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "iredges_t.h"
#include "ircons.h"
#include "irgmod.h"
+#include "irgopt.h"
#include "bitset.h"
#include "debug.h"
long node_pos = pos == -1 ? 0 : pos;
ir_mode *mode = get_irn_mode(irn);
firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
- const ia32_irn_ops_t *ops = self;
if (mode == mode_T || mode == mode_M) {
DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
}
static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
- int pos = 0;
+ int pos = 0;
+ const ia32_irn_ops_t *ops = self;
+
+ DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
if (is_Proj(irn)) {
pos = ia32_translate_proj_pos(irn);
irn = my_skip_proj(irn);
if (is_cfop(irn))
return arch_irn_class_branch;
- else if (is_ia32_Call(irn))
- return arch_irn_class_call;
else if (is_ia32_irn(irn))
return arch_irn_class_normal;
else
}
}
-static entity *ia32_get_frame_entity(const void *self, const ir_node *irn)
-{
- /* TODO: Implement */
- return NULL;
+static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
+ return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
}
static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
- if (is_ia32_use_frame(irn)) {
- /* TODO: correct offset */
+ char buf[64];
+ const ia32_irn_ops_t *ops = self;
+
+ if (is_ia32_use_frame(irn) && bias != 0) {
+ ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
+
+ DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
+ snprintf(buf, sizeof(buf), "%d", bias);
+ add_ia32_am_offs(irn, buf);
+ am_flav |= ia32_O;
+ set_ia32_am_flavour(irn, am_flav);
+ }
+}
+
+typedef struct {
+ be_abi_call_flags_bits_t flags;
+ const arch_isa_t *isa;
+ ir_graph *irg;
+} ia32_abi_env_t;
+
+static void *ia32_abi_init(const be_abi_call_t *call, const arch_isa_t *isa, ir_graph *irg)
+{
+ ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
+ be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+ env->flags = fl.bits;
+ env->irg = irg;
+ env->isa = isa;
+ return env;
+}
+
+static void ia32_abi_dont_save_regs(void *self, pset *s)
+{
+ ia32_abi_env_t *env = self;
+ if(env->flags.try_omit_fp)
+ pset_insert_ptr(s, env->isa->bp);
+}
+
+static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+{
+ ia32_abi_env_t *env = self;
+ const arch_register_t *frame_reg = env->isa->sp;
+
+ if(!env->flags.try_omit_fp) {
+ int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
+ ir_node *bl = get_irg_start_block(env->irg);
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
+ ir_node *store_bp;
+
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along);
+ store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
+ set_ia32_am_support(store_bp, ia32_am_Dest);
+ set_ia32_am_flavour(store_bp, ia32_B);
+ set_ia32_op_type(store_bp, ia32_AddrModeD);
+ *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
+ curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
+ be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
+ be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
+
+ be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
+ be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+ }
+
+ return frame_reg;
+}
+
+static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
+{
+ ia32_abi_env_t *env = self;
+ ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
+ ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+ ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
+
+ if(env->flags.try_omit_fp) {
+ curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
+ }
+
+ else {
+ ir_node *load_bp;
+ ir_mode *mode_bp = env->isa->bp->reg_class->mode;
+
+ curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
+ load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
+ set_ia32_am_support(load_bp, ia32_am_Source);
+ set_ia32_am_flavour(load_bp, ia32_B);
+ set_ia32_op_type(load_bp, ia32_AddrModeS);
+ set_ia32_ls_mode(load_bp, mode_bp);
+ curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
+ *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
+ }
+
+ be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
+ be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+}
+
+/**
+ * Produces the type which sits between the stack args and the locals on the stack.
+ * it will contain the return address and space to store the old base pointer.
+ * @return The Firm type modeling the ABI between type.
+ */
+static ir_type *ia32_abi_get_between_type(void *self)
+{
+ static ir_type *omit_fp_between_type = NULL;
+ static ir_type *between_type = NULL;
+
+ ia32_abi_env_t *env = self;
+
+ if(!between_type) {
+ entity *old_bp_ent;
+ entity *ret_addr_ent;
+ entity *omit_fp_ret_addr_ent;
+
+ ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
+ ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
+
+ between_type = new_type_class(new_id_from_str("ia32_between_type"));
+ old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
+ ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
+
+ set_entity_offset_bytes(old_bp_ent, 0);
+ set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
+ set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
+
+ omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
+ omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
+
+ set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
+ set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
}
+
+ return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
}
+static const be_abi_callbacks_t ia32_abi_callbacks = {
+ ia32_abi_init,
+ free,
+ ia32_abi_get_between_type,
+ ia32_abi_dont_save_regs,
+ ia32_abi_prologue,
+ ia32_abi_epilogue,
+};
+
/* fill register allocator interface */
static const arch_irn_ops_if_t ia32_irn_ops_if = {
*/
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
+ firm_dbg_module_t *old_mod = cg->mod;
+
+ cg->mod = firm_dbg_register("firm.be.ia32.transform");
+ irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
+ be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
- irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
- dump_ir_block_graph_sched(cg->irg, "-transformed");
edges_deactivate(cg->irg);
+ dead_node_elimination(cg->irg);
edges_activate(cg->irg);
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
- dump_ir_block_graph_sched(cg->irg, "-am");
+
+ cg->mod = old_mod;
+
+ if (cg->opt.doam) {
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
+ be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
+ }
}
+/**
+ * Insert copies for all ia32 nodes where the should_be_same requirement
+ * is not fulfilled.
+ * Transform Sub into Neg -- Add if IN2 == OUT
+ */
+static void ia32_finish_irg_walker(ir_node *irn, void *env) {
+ ia32_code_gen_t *cg = env;
+ const ia32_register_req_t **reqs;
+ const arch_register_t *out_reg, *in_reg;
+ int n_res, i;
+ ir_node *copy, *in_node, *block;
+
+ if (! is_ia32_irn(irn))
+ return;
+
+ /* nodes with destination address mode don't produce values */
+ if (get_ia32_op_type(irn) == ia32_AddrModeD)
+ return;
+
+ reqs = get_ia32_out_req_all(irn);
+ n_res = get_ia32_n_res(irn);
+ block = get_nodes_block(irn);
+
+ /* check all OUT requirements, if there is a should_be_same */
+ for (i = 0; i < n_res; i++) {
+ if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
+ /* get in and out register */
+ out_reg = get_ia32_out_reg(irn, i);
+ in_node = get_irn_n(irn, reqs[i]->same_pos);
+ in_reg = arch_get_irn_register(cg->arch_env, in_node);
+
+ /* check if in and out register are equal */
+ if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
+ DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
+
+ /* create copy from in register */
+ copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
+
+ /* destination is the out register */
+ arch_set_irn_register(cg->arch_env, copy, out_reg);
+
+ /* insert copy before the node into the schedule */
+ sched_add_before(irn, copy);
+
+ /* set copy as in */
+ set_irn_n(irn, reqs[i]->same_pos, copy);
+ }
+ }
+ }
+
+ /* check if there is a sub which need to be transformed */
+ ia32_transform_sub_to_neg_add(irn, cg);
+}
/**
- * Stack reservation and StackParam lowering.
+ * Add Copy nodes for not fulfilled should_be_equal constraints
*/
static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
-
+ irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
}
+/**
+ * Transforms a be node into a Load.
+ */
+static void transform_to_Load(ia32_transform_env_t *env) {
+ ir_node *irn = env->irn;
+ entity *ent = be_get_frame_entity(irn);
+ ir_mode *mode = env->mode;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_node *sched_point = NULL;
+ ir_node *ptr = get_irn_n(irn, 0);
+ ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
+ ir_node *new_op, *proj;
+ const arch_register_t *reg;
+
+ if (sched_is_scheduled(irn)) {
+ sched_point = sched_prev(irn);
+ }
+
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+ else {
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
+
+ if (sched_point) {
+ sched_add_after(sched_point, new_op);
+ sched_add_after(new_op, proj);
+
+ sched_remove(irn);
+ }
+
+ /* copy the register from the old node to the new Load */
+ reg = arch_get_irn_register(env->cg->arch_env, irn);
+ arch_set_irn_register(env->cg->arch_env, new_op, reg);
+
+ exchange(irn, proj);
+
+}
+
+/**
+ * Transforms a be node into a Store.
+ */
+static void transform_to_Store(ia32_transform_env_t *env) {
+ ir_node *irn = env->irn;
+ entity *ent = be_get_frame_entity(irn);
+ ir_mode *mode = env->mode;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_node *ptr = get_irn_n(irn, 0);
+ ir_node *val = get_irn_n(irn, 1);
+ ir_node *new_op, *proj;
+ ir_node *sched_point = NULL;
+
+ if (sched_is_scheduled(irn)) {
+ sched_point = sched_prev(irn);
+ }
+
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ }
+ else if (get_mode_size_bits(mode) == 8) {
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ }
+ else {
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+
+ if (sched_point) {
+ sched_add_after(sched_point, new_op);
+ sched_add_after(new_op, proj);
+
+ sched_remove(irn);
+ }
+
+ exchange(irn, proj);
+
+}
+
+/**
+ * Calls the transform functions for StackParam, Spill and Reload.
+ */
+static void ia32_after_ra_walker(ir_node *node, void *env) {
+ ia32_code_gen_t *cg = env;
+ ia32_transform_env_t tenv;
+
+ if (is_Block(node))
+ return;
+
+ tenv.block = get_nodes_block(node);
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irg = current_ir_graph;
+ tenv.irn = node;
+ tenv.mod = cg->mod;
+ tenv.mode = get_irn_mode(node);
+ tenv.cg = cg;
+
+ /* be_is_StackParam(node) || */
+ if (be_is_Reload(node)) {
+ transform_to_Load(&tenv);
+ }
+ else if (be_is_Spill(node)) {
+ transform_to_Store(&tenv);
+ }
+}
+
+/**
+ * We transform StackParam, Spill and Reload here. This needs to be done before
+ * stack biasing otherwise we would miss the corrected offset for these nodes.
+ */
+static void ia32_after_ra(void *self) {
+ ia32_code_gen_t *cg = self;
+ irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
+}
+
+
/**
* Emits the code, closes the output file and frees
* the code generator interface.
ir_graph *irg = cg->irg;
FILE *out = cg->out;
- ia32_register_emitters();
-
if (cg->emit_decls) {
ia32_gen_decls(cg->out);
cg->emit_decls = 0;
}
ia32_finish_irg(irg, cg);
- //dump_ir_block_graph_sched(irg, "-finished");
+ be_dump(irg, "-finished", dump_ir_block_graph_sched);
ia32_gen_routine(out, irg, cg);
cur_reg_set = NULL;
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
+ NULL, /* before abi introduce hook */
ia32_prepare_graph,
ia32_before_sched, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
+ ia32_after_ra, /* after register allocation hook */
ia32_codegen /* emit && done */
};
cg->tv_ent = pmap_create();
cg->birg = birg;
+ /* set optimizations */
+ cg->opt.incdec = 0;
+ cg->opt.doam = 1;
+ cg->opt.placecnst = 1;
+ cg->opt.immops = 1;
+
+#ifndef NDEBUG
+ if (isa->name_obst_size) {
+ //printf("freed %d bytes from name obst\n", isa->name_obst_size);
+ isa->name_obst_size = 0;
+ obstack_free(isa->name_obst, NULL);
+ obstack_init(isa->name_obst);
+ }
+#endif /* NDEBUG */
+
isa->num_codegens++;
if (isa->num_codegens > 1)
*****************************************************************/
static ia32_isa_t ia32_isa_template = {
- &ia32_isa_if,
- &ia32_gp_regs[REG_ESP],
- &ia32_gp_regs[REG_EBP],
- -1,
- 0
+ &ia32_isa_if, /* isa interface implementation */
+ &ia32_gp_regs[REG_ESP], /* stack pointer register */
+ &ia32_gp_regs[REG_EBP], /* base pointer register */
+ -1, /* stack direction */
+ 0, /* number of code generator objects so far */
+ NULL, /* 16bit register names */
+ NULL, /* 8bit register names */
+#ifndef NDEBUG
+ NULL, /* name obstack */
+ 0 /* name obst size */
+#endif
};
/**
ia32_register_init(isa);
ia32_create_opcodes();
+ isa->regs_16bit = pmap_create();
+ isa->regs_8bit = pmap_create();
+
+ ia32_build_16bit_reg_map(isa->regs_16bit);
+ ia32_build_8bit_reg_map(isa->regs_8bit);
+
+#ifndef NDEBUG
+ isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
+ obstack_init(isa->name_obst);
+ isa->name_obst_size = 0;
+#endif /* NDEBUG */
+
inited = 1;
return isa;
* Closes the output file and frees the ISA structure.
*/
static void ia32_done(void *self) {
+ ia32_isa_t *isa = self;
+
+ pmap_destroy(isa->regs_16bit);
+ pmap_destroy(isa->regs_8bit);
+
+#ifndef NDEBUG
+ //printf("name obst size = %d bytes\n", isa->name_obst_size);
+ obstack_free(isa->name_obst, NULL);
+#endif /* NDEBUG */
+
free(self);
}
return &ia32_reg_classes[CLASS_ia32_gp];
}
-/**
- * Produces the type which sits between the stack args and the locals on the stack.
- * it will contain the return address and space to store the old base pointer.
- * @return The Firm type modelling the ABI between type.
- */
-static ir_type *get_between_type(void)
-{
- static ir_type *between_type = NULL;
- static entity *old_bp_ent = NULL;
-
- if(!between_type) {
- entity *ret_addr_ent;
- ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
- ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
-
- between_type = new_type_class(new_id_from_str("ia32_between_type"));
- old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
- ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
-
- set_entity_offset_bytes(old_bp_ent, 0);
- set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
- set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
- }
-
- return between_type;
-}
-
/**
* Get the ABI restrictions for procedure calls.
* @param self The this pointer.
* @param abi The abi object to be modified
*/
void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
- ir_type *between_type;
ir_type *tp;
ir_mode *mode;
unsigned cc = get_method_calling_convention(method_type);
int n = get_method_n_params(method_type);
int biggest_n = -1;
int stack_idx = 0;
- int i, ignore;
+ int i, ignore_1, ignore_2;
ir_mode **modes;
const arch_register_t *reg;
- be_abi_call_flags_t call_flags = { 0, 0, 1, 0, 1 };
+ be_abi_call_flags_t call_flags;
- /* get the between type and the frame pointer save entity */
- between_type = get_between_type();
+ /* set abi flags for calls */
+ call_flags.bits.left_to_right = 0;
+ call_flags.bits.store_args_sequential = 0;
+ call_flags.bits.try_omit_fp = 1;
+ call_flags.bits.fp_free = 0;
+ call_flags.bits.call_has_imm = 1;
/* set stack parameter passing style */
- be_abi_call_set_flags(abi, call_flags, between_type);
+ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
/* collect the mode for each type */
modes = alloca(n * sizeof(modes[0]));
/* set register parameters */
if (cc & cc_reg_param) {
/* determine the number of parameters passed via registers */
- biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
+ biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
/* loop over all parameters and set the register requirements */
for (i = 0; i <= biggest_n; i++) {
}
else if (n == 1) {
tp = get_method_res_type(method_type, 0);
+ assert(is_atomic_type(tp));
mode = get_type_mode(tp);
- be_abi_call_res_reg(abi, 0, &ia32_fp_regs[mode_is_float(mode) ? REG_XMM0 : REG_EAX]);
+ be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
}
}
* Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
*/
static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
- memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
+ memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
return &ia32_sched_selector;
}
projects / libfirm / blobdiff