-/**
- * This is the main ia32 firm backend driver.
- * @author Christian Wuerdig
- * $Id$
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
*/
+/**
+ * @file
+ * @brief This is the main ia32 firm backend driver.
+ * @author Christian Wuerdig
+ * @version $Id$
+ */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
-#ifdef HAVE_MALLOC_H
-#include <malloc.h>
-#endif
-
-#ifdef HAVE_ALLOCA_H
-#include <alloca.h>
-#endif
-
-#ifdef WITH_LIBCORE
#include <libcore/lc_opts.h>
#include <libcore/lc_opts_enum.h>
-#endif /* WITH_LIBCORE */
#include <math.h>
#include "irgmod.h"
#include "irgopt.h"
#include "irbitset.h"
+#include "irgopt.h"
#include "pdeq.h"
#include "pset.h"
#include "debug.h"
+#include "error.h"
+#include "xmalloc.h"
-#include "../beabi.h" /* the general register allocator interface */
+#include "../beabi.h"
+#include "../beirg_t.h"
#include "../benode_t.h"
#include "../belower.h"
#include "../besched_t.h"
#include "../beilpsched.h"
#include "../bespillslots.h"
#include "../bemodule.h"
+#include "../begnuas.h"
+#include "../bestate.h"
#include "bearch_ia32_t.h"
-#include "ia32_new_nodes.h" /* ia32 nodes interface */
-#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
+#include "ia32_new_nodes.h"
+#include "gen_ia32_regalloc_if.h"
#include "gen_ia32_machine.h"
-#include "ia32_gen_decls.h" /* interface declaration emitter */
#include "ia32_transform.h"
#include "ia32_emitter.h"
#include "ia32_map_regs.h"
#include "ia32_dbg_stat.h"
#include "ia32_finish.h"
#include "ia32_util.h"
+#include "ia32_fpu.h"
-#define DEBUG_MODULE "firm.be.ia32.isa"
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/* TODO: ugly */
static set *cur_reg_set = NULL;
+ir_mode *mode_fpcw = NULL;
+
typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
- create_const_node_func func, arch_register_t* reg)
+ create_const_node_func func,
+ const arch_register_t* reg)
{
ir_node *block, *res;
- ir_node *startnode;
if(*place != NULL)
return *place;
arch_set_irn_register(cg->arch_env, res, reg);
*place = res;
- startnode = get_irg_start(cg->irg);
- if(sched_is_scheduled(startnode)) {
- sched_add_before(startnode, res);
- }
+ add_irn_dep(get_irg_end(cg->irg), res);
+ /* add_irn_dep(get_irg_start(cg->irg), res); */
return res;
}
&ia32_xmm_regs[REG_XMM_UKNWN]);
}
+ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
+ return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
+ &ia32_fp_cw_regs[REG_FPCW]);
+}
+
/**
* Returns gp_noreg or fp_noreg, depending in input requirements.
*/
ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
- arch_register_req_t req;
- const arch_register_req_t *p_req;
+ const arch_register_req_t *req;
- p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
- assert(p_req && "Missing register requirements");
- if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
+ req = arch_get_register_req(cg->arch_env, irn, pos);
+ assert(req != NULL && "Missing register requirements");
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
return ia32_new_NoReg_gp(cg);
- else
- return ia32_new_NoReg_fp(cg);
+
+ return ia32_new_NoReg_fp(cg);
}
/**************************************************
* If the node returns a tuple (mode_T) then the proj's
* will be asked for this information.
*/
-static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
- const ia32_irn_ops_t *ops = self;
- const ia32_register_req_t *irn_req;
- long node_pos = pos == -1 ? 0 : pos;
- ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
- FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
-
- if (is_Block(irn) || mode == mode_X) {
- DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
- return NULL;
+static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
+ const ir_node *node,
+ int pos) {
+ long node_pos = pos == -1 ? 0 : pos;
+ ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
+
+ if (is_Block(node) || mode == mode_X) {
+ return arch_no_register_req;
}
if (mode == mode_T && pos < 0) {
- DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
- return NULL;
+ return arch_no_register_req;
}
- DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
-
- if (is_Proj(irn)) {
+ if (is_Proj(node)) {
if(mode == mode_M)
- return NULL;
+ return arch_no_register_req;
if(pos >= 0) {
- DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
- return NULL;
+ return arch_no_register_req;
}
- node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
- irn = skip_Proj_const(irn);
-
- DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
+ node = skip_Proj_const(node);
}
- if (is_ia32_irn(irn)) {
- irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
- if (irn_req == NULL) {
- /* no requirements */
- return NULL;
- }
-
- DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
+ if (is_ia32_irn(node)) {
+ const arch_register_req_t *req;
+ if(pos >= 0)
+ req = get_ia32_in_req(node, pos);
+ else
+ req = get_ia32_out_req(node, node_pos);
- memcpy(req, &(irn_req->req), sizeof(*req));
+ assert(req != NULL);
- if (arch_register_req_is(&(irn_req->req), should_be_same)) {
- assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
- req->other_same = get_irn_n(irn, irn_req->same_pos);
- }
-
- if (arch_register_req_is(&(irn_req->req), should_be_different)) {
- assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
- req->other_different = get_irn_n(irn, irn_req->different_pos);
- }
- }
- else {
- /* treat Unknowns like Const with default requirements */
- if (is_Unknown(irn)) {
- DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
- if (mode_is_float(mode)) {
- if (USE_SSE2(ops->cg))
- memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
- else
- memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
- }
- else if (mode_is_int(mode) || mode_is_reference(mode))
- memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
- else if (mode == mode_T || mode == mode_M) {
- DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
- return NULL;
- }
- else
- assert(0 && "unsupported Unknown-Mode");
- }
- else {
- DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
- req = NULL;
- }
+ return req;
}
- return req;
+ /* unknowns should be transformed already */
+ assert(!is_Unknown(node));
+
+ return arch_no_register_req;
}
static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
int pos = 0;
- const ia32_irn_ops_t *ops = self;
if (get_irn_mode(irn) == mode_X) {
return;
}
- DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
-
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = skip_Proj(irn);
slots = get_ia32_slots(irn);
slots[pos] = reg;
- }
- else {
+ } else {
ia32_set_firm_reg(irn, reg, cur_reg_set);
}
}
const arch_register_t **slots;
slots = get_ia32_slots(irn);
reg = slots[pos];
- }
- else {
+ } else {
reg = ia32_get_firm_reg(irn, cur_reg_set);
}
if (is_ia32_Ld(irn))
classification |= arch_irn_class_load;
- if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+ if (is_ia32_St(irn))
classification |= arch_irn_class_store;
- if (is_ia32_got_reload(irn))
+ if (is_ia32_need_stackent(irn))
classification |= arch_irn_class_reload;
return classification;
}
}
- DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
-
am_flav = get_ia32_am_flavour(irn);
am_flav |= ia32_O;
set_ia32_am_flavour(irn, am_flav);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *push;
+ /* ALL nodes representing bp must be set to ignore. */
+ be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
+
/* push ebp */
push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
inverse->costs += 1;
}
break;
- case iro_ia32_Eor:
+ case iro_ia32_Xor:
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
- inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
- inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
+ inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
inverse->costs += 1;
}
break;
inverse->costs += 1;
break;
}
- case iro_ia32_Minus: {
- inverse->nodes[0] = new_rd_ia32_Minus(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
+ case iro_ia32_Neg: {
+ inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
inverse->costs += 1;
break;
}
return inverse;
}
+static ir_mode *get_spill_mode_mode(const ir_mode *mode)
+{
+ if(mode_is_float(mode))
+ return mode_D;
+
+ return mode_Iu;
+}
+
/**
* Get the mode that should be used for spilling value node
*/
-static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node)
+static ir_mode *get_spill_mode(const ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
- if (mode_is_float(mode)) {
-#if 0
- // super exact spilling...
- if (USE_SSE2(cg))
- return mode_D;
- else
- return mode_E;
-#else
- return mode_D;
-#endif
- }
- else
- return mode_Is;
-
- assert(0);
- return mode;
+ return get_spill_mode_mode(mode);
}
/**
* @return Non-Zero if operand can be loaded
*/
static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
- const ia32_irn_ops_t *ops = self;
- ia32_code_gen_t *cg = ops->cg;
ir_node *op = get_irn_n(irn, i);
const ir_mode *mode = get_irn_mode(op);
- const ir_mode *spillmode = get_spill_mode(cg, op);
+ const ir_mode *spillmode = get_spill_mode(op);
if (! is_ia32_irn(irn) || /* must be an ia32 irn */
get_irn_arity(irn) != 5 || /* must be a binary operation */
set_ia32_am_flavour(irn, ia32_B);
set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
set_ia32_use_frame(irn);
- set_ia32_got_reload(irn);
+ set_ia32_need_stackent(irn);
set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
ia32_abi_get_between_type,
ia32_abi_dont_save_regs,
ia32_abi_prologue,
- ia32_abi_epilogue,
+ ia32_abi_epilogue
};
/* fill register allocator interface */
* |___/
**************************************************/
-/**
- * Transform the Thread Local Store base.
- */
-static void transform_tls(ir_graph *irg) {
- ir_node *irn = get_irg_tls(irg);
-
- if (irn) {
- dbg_info *dbg = get_irn_dbg_info(irn);
- ir_node *blk = get_nodes_block(irn);
- ir_node *newn;
- newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
-
- exchange(irn, newn);
- set_irg_tls(irg, newn);
- }
-}
-
/**
* Transforms the standard firm graph into
* an ia32 firm graph
*/
static void ia32_prepare_graph(void *self) {
ia32_code_gen_t *cg = self;
- DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
-
- /* 1st: transform constants and psi condition trees */
+ /* transform psi condition trees */
ia32_pre_transform_phase(cg);
- /* 2nd: transform all remaining nodes */
- transform_tls(cg->irg);
+ /* transform all remaining nodes */
ia32_transform_graph(cg);
+ //add_fpu_edges(cg->birg);
+
// Matze: disabled for now. Because after transformation start block has no
- // self-loop anymore so it will probably melt with its successor block.
- //
- // This will bring several nodes to the startblock and we still can't
- // handle spill before the initial IncSP nicely
- //local_optimize_graph(cg->irg);
+ // self-loop anymore so it might be merged with its successor block. This
+ // will bring several nodes to the startblock which sometimes get scheduled
+ // before the initial IncSP/Barrier
+ local_optimize_graph(cg->irg);
if (cg->dump)
be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
- /* 3rd: optimize address mode */
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
- ia32_optimize_addressmode(cg);
+ /* optimize address mode */
+ ia32_optimize_graph(cg);
if (cg->dump)
be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
- DEBUG_ONLY(cg->mod = old_mod;)
+ /* do code placement, to optimize the position of constants */
+ place_code(cg->irg);
+
+ if (cg->dump)
+ be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
}
/**
after removing the Load from schedule.
*/
irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
+
+ /* setup fpu rounding modes */
+ ia32_setup_fpu_mode(cg);
}
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node);
- ir_mode *spillmode = get_spill_mode(cg, node);
+ ir_mode *spillmode = get_spill_mode(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(irg);
else
new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
}
+ else if (get_mode_size_bits(spillmode) == 128) {
+ // Reload 128 bit sse registers
+ new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
+ }
else
new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node);
const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
- ir_mode *mode = get_spill_mode(cg, spillval);
+ ir_mode *mode = get_spill_mode(spillval);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *nomem = new_rd_NoMem(irg);
ir_node *ptr = get_irg_frame(irg);
sched_point = sched_prev(node);
}
+ /* No need to spill unknown values... */
+ if(is_ia32_Unknown_GP(val) ||
+ is_ia32_Unknown_VFP(val) ||
+ is_ia32_Unknown_XMM(val)) {
+ store = nomem;
+ if(sched_point)
+ sched_remove(node);
+
+ exchange(node, store);
+ return;
+ }
+
if (mode_is_float(mode)) {
if (USE_SSE2(cg))
store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
else
store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else if (get_mode_size_bits(mode) == 8) {
+ } else if (get_mode_size_bits(mode) == 128) {
+ // Spill 128 bit SSE registers
+ store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
+ } else if (get_mode_size_bits(mode) == 8) {
store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
- }
- else {
+ } else {
store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
}
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
-
- DBG_OPT_SPILL2ST(node, store);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
+ DBG_OPT_SPILL2ST(node, store);
if (sched_point) {
sched_add_after(sched_point, store);
// create pushs
for(i = 0; i < arity; ++i) {
- ir_entity *ent = be_get_MemPerm_in_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(inent);
int entbits = get_type_size_bits(enttype);
+ int entbits2 = get_type_size_bits(get_entity_type(outent));
ir_node *mem = get_irn_n(node, i + 1);
ir_node *push;
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- push = create_push(cg, node, node, sp, mem, ent);
+ push = create_push(cg, node, node, sp, mem, inent);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
if(entbits == 64) {
// add another push after the first one
- push = create_push(cg, node, node, sp, mem, ent);
+ push = create_push(cg, node, node, sp, mem, inent);
add_ia32_am_offs_int(push, 4);
sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
}
// create pops
for(i = arity - 1; i >= 0; --i) {
- ir_entity *ent = be_get_MemPerm_out_entity(node, i);
- ir_type *enttype = get_entity_type(ent);
+ ir_entity *inent = be_get_MemPerm_in_entity(node, i);
+ ir_entity *outent = be_get_MemPerm_out_entity(node, i);
+ ir_type *enttype = get_entity_type(outent);
int entbits = get_type_size_bits(enttype);
-
+ int entbits2 = get_type_size_bits(get_entity_type(inent));
ir_node *pop;
+ /* work around cases where entities have different sizes */
+ if(entbits2 < entbits)
+ entbits = entbits2;
assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
- pop = create_pop(cg, node, node, sp, ent);
+ pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
if(entbits == 64) {
add_ia32_am_offs_int(pop, 4);
// add another pop after the first one
- pop = create_pop(cg, node, node, sp, ent);
+ pop = create_pop(cg, node, node, sp, outent);
sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
}
be_fec_env_t *env = data;
if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
- const ir_mode *mode = get_irn_mode(node);
+ const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
int align = get_mode_size_bytes(mode);
be_node_needs_frame_entity(env, node, mode, align);
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) {
- if (is_ia32_Load(node)) {
+ if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
const ir_mode *mode = get_ia32_ls_mode(node);
int align = get_mode_size_bytes(mode);
be_node_needs_frame_entity(env, node, mode, align);
- } else if (is_ia32_vfild(node)) {
+ } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
const ir_mode *mode = get_ia32_ls_mode(node);
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
+ } else if(is_ia32_FldCW(node)) {
+ const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
+ int align = 4;
+ be_node_needs_frame_entity(env, node, mode, align);
} else if (is_ia32_SetST0(node)) {
const ir_mode *mode = get_ia32_ls_mode(node);
int align = 4;
be_node_needs_frame_entity(env, node, mode, align);
} else {
#ifndef NDEBUG
- if(!is_ia32_Store(node)
- && !is_ia32_xStore(node)
- && !is_ia32_xStoreSimple(node)
- && !is_ia32_vfist(node)) {
+ if(!is_ia32_St(node) && !is_ia32_xStoreSimple(node)
+ && !is_ia32_vfist(node)
+ && !is_ia32_GetST0(node)
+ && !is_ia32_FnstCW(node)) {
assert(0);
}
#endif
ia32_code_gen_t *cg = self;
ir_graph *irg = cg->irg;
- ia32_gen_routine(cg->isa->out, irg, cg);
+ ia32_gen_routine(cg, irg);
cur_reg_set = NULL;
cg->used_fp = fp_none;
cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
- FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
-
/* copy optimizations from isa for easier access */
cg->opt = isa->opt;
cg->arch = isa->arch;
-1, /* stack direction */
NULL, /* main environment */
},
+ { NULL, }, /* emitter environment */
NULL, /* 16bit register names */
NULL, /* 8bit register names */
NULL, /* types */
arch_pentium_4, /* optimize for architecture */
fp_sse2, /* use sse2 unit */
NULL, /* current code generator */
- NULL, /* output file */
#ifndef NDEBUG
NULL, /* name obstack */
0 /* name obst size */
if (inited)
return NULL;
+ inited = 1;
set_tarval_output_modes();
isa = xmalloc(sizeof(*isa));
memcpy(isa, &ia32_isa_template, sizeof(*isa));
+ if(mode_fpcw == NULL) {
+ mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+ }
+
ia32_register_init(isa);
ia32_create_opcodes();
ia32_register_copy_attr_func();
isa->opt &= ~IA32_OPT_INCDEC;
}
+ be_emit_init_env(&isa->emit, file_handle);
isa->regs_16bit = pmap_create();
isa->regs_8bit = pmap_create();
isa->types = pmap_create();
isa->tv_ent = pmap_create();
- isa->out = file_handle;
isa->cpu = ia32_init_machine_description();
ia32_build_16bit_reg_map(isa->regs_16bit);
ia32_build_8bit_reg_map(isa->regs_8bit);
- /* patch register names of x87 registers */
- ia32_st_regs[0].name = "st";
- ia32_st_regs[1].name = "st(1)";
- ia32_st_regs[2].name = "st(2)";
- ia32_st_regs[3].name = "st(3)";
- ia32_st_regs[4].name = "st(4)";
- ia32_st_regs[5].name = "st(5)";
- ia32_st_regs[6].name = "st(6)";
- ia32_st_regs[7].name = "st(7)";
-
#ifndef NDEBUG
isa->name_obst = xmalloc(sizeof(*isa->name_obst));
obstack_init(isa->name_obst);
#endif /* NDEBUG */
ia32_handle_intrinsics();
- ia32_switch_section(isa->out, NO_SECTION);
- fprintf(isa->out, "\t.intel_syntax\n");
/* needed for the debug support */
- ia32_switch_section(isa->out, SECTION_TEXT);
- fprintf(isa->out, ".Ltext0:\n");
+ be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
+ be_emit_cstring(&isa->emit, ".Ltext0:\n");
+ be_emit_write_line(&isa->emit);
- inited = 1;
+ /* we mark referenced global entities, so we can only emit those which
+ * are actually referenced. (Note: you mustn't use the type visited flag
+ * elsewhere in the backend)
+ */
+ inc_master_type_visited();
return isa;
}
ia32_isa_t *isa = self;
/* emit now all global declarations */
- ia32_gen_decls(isa->out, isa->arch_isa.main_env);
+ be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
pmap_destroy(isa->regs_16bit);
pmap_destroy(isa->regs_8bit);
obstack_free(isa->name_obst, NULL);
#endif /* NDEBUG */
+ be_emit_destroy_env(&isa->emit);
+
free(self);
}
* - the general purpose registers
* - the SSE floating point register set
* - the virtual floating point registers
+ * - the SSE vector register set
*/
static int ia32_get_n_reg_class(const void *self) {
- return 3;
+ return N_CLASSES;
}
/**
* Return the register class for index i.
*/
-static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
- assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
- if (i == 0)
- return &ia32_reg_classes[CLASS_ia32_gp];
- else if (i == 1)
- return &ia32_reg_classes[CLASS_ia32_xmm];
- else
- return &ia32_reg_classes[CLASS_ia32_vfp];
+static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
+{
+ assert(i >= 0 && i < N_CLASSES);
+ return &ia32_reg_classes[i];
}
/**
}
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
- return is_ia32_irn(irn) ? 1 : -1;
+ if(!is_ia32_irn(irn))
+ return -1;
+
+ if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
+ || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
+ || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn))
+ return 0;
+
+ return 1;
}
/**
p.if_conv_info = &ifconv;
return &p;
}
-#ifdef WITH_LIBCORE
/* instruction set architectures. */
static const lc_opt_enum_int_items_t arch_items[] = {
};
static const lc_opt_enum_int_items_t gas_items[] = {
- { "linux", ASM_LINUX_GAS },
- { "mingw", ASM_MINGW_GAS },
+ { "normal", GAS_FLAVOUR_NORMAL },
+ { "mingw", GAS_FLAVOUR_MINGW },
{ NULL, 0 }
};
static lc_opt_enum_int_var_t gas_var = {
- (int *)&asm_flavour, gas_items
+ (int*) &be_gas_flavour, gas_items
};
static const lc_opt_table_entry_t ia32_options[] = {
LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
{ NULL }
};
-#endif /* WITH_LIBCORE */
const arch_isa_if_t ia32_isa_if = {
ia32_init,
ia32_get_irg_list,
};
+void ia32_init_emitter(void);
+void ia32_init_finish(void);
+void ia32_init_optimize(void);
+void ia32_init_transform(void);
+void ia32_init_x87(void);
+
void be_init_arch_ia32(void)
{
lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
lc_opt_add_table(ia32_grp, ia32_options);
be_register_isa_if("ia32", &ia32_isa_if);
+
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
+
+ ia32_init_emitter();
+ ia32_init_finish();
+ ia32_init_optimize();
+ ia32_init_transform();
+ ia32_init_x87();
}
BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
projects / libfirm / blobdiff