#include "config.h"
#endif
+#ifdef _WIN32
+#include <malloc.h>
+#else
+#include <alloca.h>
+#endif
+
#include "pseudo_irg.h"
#include "irgwalk.h"
#include "irprog.h"
#include "irprintf.h"
#include "iredges_t.h"
+#include "ircons.h"
+#include "irgmod.h"
#include "bitset.h"
#include "debug.h"
#include "../bearch.h" /* the general register allocator interface */
#include "../benode_t.h"
+#include "../belower.h"
+#include "../besched_t.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h" /* ia32 nodes interface */
#include "ia32_transform.h"
#include "ia32_emitter.h"
#include "ia32_map_regs.h"
+#include "ia32_optimize.h"
-#define DEBUG_MODULE "ir.be.isa.ia32"
+#define DEBUG_MODULE "firm.be.ia32.isa"
/* TODO: ugly */
static set *cur_reg_set = NULL;
static int is_P_frame_base_Proj(const ir_node *n) {
if (is_Proj(n) &&
- is_Start(n) &&
+ is_Start(get_Proj_pred(n)) &&
get_Proj_proj(n) == pn_Start_P_frame_base)
{
return 1;
if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
- irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
- memcpy(req, &(irn_req->req), sizeof(*req));
+ if (pos >= 0) {
+ req = NULL;
+ }
+ else {
+ irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
+ memcpy(req, &(irn_req->req), sizeof(*req));
+ }
+
return req;
}
else if (is_Start_Proj(irn)) {
irn = my_skip_proj(irn);
- DBG((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+ DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
}
if (is_ia32_irn(irn)) {
irn_req = get_ia32_out_req(irn, node_pos);
}
- DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
+ DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
memcpy(req, &(irn_req->req), sizeof(*req));
else {
/* treat Phi like Const with default requirements */
if (is_Phi(irn)) {
- DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
+ DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
if (mode_is_float(mode))
memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
else if (mode_is_int(mode) || mode_is_reference(mode))
assert(0 && "unsupported Phi-Mode");
}
else if (is_Start(irn)) {
- DBG((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
+ DB((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
switch (node_pos) {
case pn_Start_X_initial_exec:
case pn_Start_P_value_arg_base:
}
}
else if (get_irn_op(irn) == op_Return && pos > 0) {
- DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
+ DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
}
else {
- DBG((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
+ DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
req = NULL;
}
}
if (is_ia32_irn(irn))
return get_ia32_flags(irn);
else {
- ir_printf("don't know flags of %+F\n", irn);
+ if (is_Start_Proj(irn))
+ return arch_irn_flags_ignore;
+
return 0;
}
}
static void check_for_alloca(ir_node *irn, void *env) {
int *has_alloca = env;
- if (get_irn_opcode(irn) == iro_Alloc) {
+ if (get_irn_op(irn) == op_Alloc) {
if (get_Alloc_where(irn) == stack_alloc) {
*has_alloca = 1;
}
ia32_general_purpose_regs[REG_EBP].type = arch_register_type_ignore;
}
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
+ irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
}
}
/**
- * Set the register for P_frame_base Proj to %esp.
+ * Stack reservation and StackParam lowering.
*/
-static void ia32_set_P_frame_base_Proj_reg(ir_node *irn, void *env) {
- ia32_code_gen_t *cg = env;
+static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
+ firm_dbg_module_t *mod = cg->mod;
+ ir_node *frame = get_irg_frame(irg);
+ ir_node *end_block = get_irg_end_block(irg);
+ ir_node **returns, **in, **new_in;
+ ir_node *stack_reserve, *sched_point;
+ ir_node *stack_free, *new_ret, *return_block;
+ int stack_size = 0, i, n_arg;
+ arch_register_t *stack_reg;
+ tarval *stack_size_tv;
+ dbg_info *frame_dbg;
+
+ /* Determine stack register */
+ if (cg->has_alloca) {
+ stack_reg = &ia32_general_purpose_regs[REG_EBP];
+ }
+ else {
+ stack_reg = &ia32_general_purpose_regs[REG_ESP];
+ }
+
+ /* If frame is used, then we need to reserve some stackspace. */
+ if (get_irn_n_edges(frame) > 0) {
+ /* The initial stack reservation. */
+ stack_size = get_type_size_bytes(get_irg_frame_type(irg));
+ frame_dbg = get_irn_dbg_info(frame);
+ stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
+ stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
+ set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
+
+ assert(stack_size && "bOrken stack layout");
+
+ /* reroute all edges from frame pointer to corrected frame pointer */
+ edges_reroute(frame, stack_reserve, irg);
+ set_irn_n(stack_reserve, 0, frame);
+
+ /* schedule frame pointer */
+ if (! sched_is_scheduled(frame)) {
+ sched_add_after(get_irg_start(irg), frame);
+ }
- if (is_P_frame_base_Proj(irn)) {
- arch_set_irn_register(cg->arch_env, irn, &ia32_general_purpose_regs[REG_ESP]);
+ /* set register */
+ arch_set_irn_register(cg->arch_env, frame, stack_reg);
+ arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
+
+ /* insert into schedule */
+ sched_add_after(frame, stack_reserve);
+
+ /* Free stack for each Return node */
+ returns = get_Block_cfgpred_arr(end_block);
+ for (i = 0; i < get_Block_n_cfgpreds(end_block); i++) {
+ assert(get_irn_opcode(returns[i]) == iro_Return && "cfgpred of endblock is not a return");
+
+ return_block = get_nodes_block(returns[i]);
+
+ /* free the stack */
+ stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
+ set_ia32_Immop_tarval(stack_free, stack_size_tv);
+ arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
+
+ DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
+
+ /* get the old Return arguments */
+ n_arg = get_Return_n_ress(returns[i]);
+ in = get_Return_res_arr(returns[i]);
+ new_in = xmalloc((n_arg + 2) * sizeof(new_in[0]));
+
+ if (!new_in) {
+ printf("\nMUAAAAHAHAHAHAHAHAHAH\n");
+ exit(1);
+ }
+
+ /* copy the old to the new in's */
+ memcpy(new_in, in, n_arg * sizeof(in[0]));
+ new_in[n_arg++] = stack_free;
+ new_in[n_arg++] = get_Return_mem(returns[i]);
+
+ /* create the new return node */
+ new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
+
+ /* In case the return node is the only node in the block, */
+ /* it is not scheduled, so we need this work-around. */
+ if (! sched_is_scheduled(returns[i])) {
+ sched_point = return_block;
+ }
+ else {
+ sched_point = sched_prev(returns[i]);
+ sched_remove(returns[i]);
+ }
+
+ /* exchange the old return with the new one */
+ exchange(returns[i], new_ret);
+
+ DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
+
+ /* remove the old one from schedule and add the new nodes properly */
+ sched_add_after(sched_point, new_ret);
+ sched_add_after(sched_point, stack_free);
+ }
}
}
+
+
/**
- * This function is the hook before_sched but more important: it is
- * called after the dead node elimination. The dead node elimination changes
- * the memory location of the nodes, which will change the hash key of
- * the Proj_P_frame_base(Start) and this will fuck up the firm_node -> register
- * hash map. So we need to insert the register for this node after the dead node
- * elimination.
+ * Dummy functions for hooks we don't need but which must be filled.
*/
-static void ia32_some_stuff_need_to_be_done_after_deadnode_elimination(void *self) {
- ia32_code_gen_t *cg = self;
+static void ia32_before_sched(void *self) {
+ ia32_code_gen_t *cg = self;
- if (! is_pseudo_ir_graph(cg->irg))
- irg_walk_blkwise_graph(cg->irg, NULL, ia32_set_P_frame_base_Proj_reg, cg);
+ lower_nodes_before_sched(cg->irg, cg->arch_env);
}
+static void ia32_before_ra(void *self) {
+}
/**
- * Dummy functions for hooks we don't need but which must be filled.
+ * Creates a Store for a Spill
*/
-static void ia32_before_ra(void *self) {
+static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
+ ia32_code_gen_t *cg = self;
+ dbg_info *dbg = get_irn_dbg_info(spill);
+ ir_node *block = get_nodes_block(spill);
+ ir_node *ptr = get_irg_frame(cg->irg);
+ ir_node *val = be_get_Spill_context(spill);
+ ir_node *mem = new_rd_NoMem(cg->irg);
+ ir_mode *mode = get_irn_mode(spill);
+ ir_node *res;
+ entity *ent = be_get_spill_entity(spill);
+ unsigned offs = get_entity_offset_bytes(ent);
+
+ DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
+
+ res = new_rd_ia32_Store(dbg, cg->irg, block, ptr, val, mem, mode);
+ set_ia32_am_offs(res, new_tarval_from_long(offs, mode_Iu));
+
+ return res;
}
+/**
+ * Create a Load for a Spill
+ */
+static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
+ ia32_code_gen_t *cg = self;
+ dbg_info *dbg = get_irn_dbg_info(reload);
+ ir_node *block = get_nodes_block(reload);
+ ir_node *ptr = get_irg_frame(cg->irg);
+ ir_mode *mode = get_irn_mode(reload);
+ ir_node *pred = get_irn_n(reload, 0);
+ tarval *tv;
+ ir_node *res;
+
+ if (be_is_Spill(pred)) {
+ entity *ent = be_get_spill_entity(pred);
+ unsigned offs = get_entity_offset_bytes(ent);
+ DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
+ tv = new_tarval_from_long(offs, mode_Iu);
+ }
+ else if (is_ia32_Store(pred)) {
+ tv = get_ia32_am_offs(pred);
+ }
+ else {
+ assert(0 && "unsupported Reload predecessor");
+ }
+
+ res = new_rd_ia32_Load(dbg, cg->irg, block, ptr, pred, mode);
+ set_ia32_am_offs(res, tv);
+ return res;
+}
+
+/**
+ * Return the stack register for this irg.
+ */
+static const arch_register_t *ia32_get_stack_register(void *self) {
+ ia32_code_gen_t *cg = self;
+
+ if (cg->has_alloca) {
+ return &ia32_general_purpose_regs[REG_EBP];
+ }
+
+ return &ia32_general_purpose_regs[REG_ESP];
+}
/**
* Emits the code, closes the output file and frees
cg->emit_decls = 0;
}
-// ia32_finish_irg(irg);
- ia32_gen_routine(out, irg, cg->arch_env);
+ ia32_finish_irg(irg, cg);
+ dump_ir_block_graph_sched(irg, "-finished");
+ ia32_gen_routine(out, irg, cg);
cur_reg_set = NULL;
static const arch_code_generator_if_t ia32_code_gen_if = {
ia32_cg_init,
ia32_prepare_graph,
- ia32_some_stuff_need_to_be_done_after_deadnode_elimination, /* before scheduling hook */
+ ia32_before_sched, /* before scheduling hook */
ia32_before_ra, /* before register allocation hook */
+ ia32_lower_spill,
+ ia32_lower_reload,
+ ia32_get_stack_register,
ia32_codegen /* emit && done */
};
*/
static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
- ia32_code_gen_t *cg = malloc(sizeof(*cg));
+ ia32_code_gen_t *cg = xmalloc(sizeof(*cg));
cg->impl = &ia32_code_gen_if;
cg->irg = irg;
cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
- cg->mod = firm_dbg_register("be.transform.ia32");
+ cg->mod = firm_dbg_register("firm.be.ia32.cg");
cg->out = F;
cg->arch_env = arch_env;
*/
static void *ia32_init(void) {
static int inited = 0;
- ia32_isa_t *isa = malloc(sizeof(*isa));
+ ia32_isa_t *isa = xmalloc(sizeof(*isa));
isa->impl = &ia32_isa_if;
return &ia32_irn_handler;
}
-long ia32_get_call_projnum_for_reg(const void *self, const arch_register_t *reg) {
+long ia32_handle_call_proj(const void *self, ir_node *proj, int is_keep) {
ia32_isa_t *isa = (ia32_isa_t *)self;
- return ia32_get_reg_projnum(reg, isa->reg_projnum_map);
+ long pn = get_Proj_proj(proj);
+
+ if (!is_keep) {
+ /* It's not a Keep proj, which means, that it is a result proj. */
+ /* Possible result proj numbers are 0 and 1 */
+ /* Set the correct register (depends on the mode) and the */
+ /* corresponding proj number */
+ if (mode_is_float(get_irn_mode(proj))) {
+ assert(pn == 0 && "only one floating point result supported");
+
+ /* Get the proj number for the floating point result */
+ pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_XMM0], isa->reg_projnum_map);
+ }
+ else {
+ /* In case of 64bit return value, the result is */
+ /* in EDX:EAX and we have two result projs. */
+ switch (pn) {
+ case 0:
+ pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_EAX], isa->reg_projnum_map);
+ break;
+ case 1:
+ pn = ia32_get_reg_projnum(&ia32_floating_point_regs[REG_EDX], isa->reg_projnum_map);
+ break;
+ default:
+ assert(0 && "only two int results supported");
+ }
+ }
+
+ /* Set the correct proj number */
+ set_Proj_proj(proj, pn);
+ }
+ else {
+ /* Set mode to floating point if required */
+ if (!strcmp(ia32_reg_classes[CLASS_ia32_floating_point].name,
+ ia32_projnum_reg_req_map[pn]->req.cls->name)) {
+ set_irn_mode(proj, mode_F);
+ }
+ }
+
+ return pn;
}
int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
ia32_get_irn_handler,
ia32_get_code_generator_if,
ia32_get_list_sched_selector,
- ia32_get_call_projnum_for_reg
+ ia32_handle_call_proj
};
projects / libfirm / blobdiff